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Location:
Bengaluru, KA, 560001, India
Posted:
February 26, 2016

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Resume:

SAROJINI HOOGAR S

BTM LAYOUT *ND STAGE BANGALORE, 560076 INDIA

Phone:-+91-702*******/ +91-944******* Email: - acto97@r.postjobfree.com

CAREER OBJECTIVE:

Aiming for a position to best utilize my skills in an environment which offers opportunities for professional & personal growth and help me to continue achieving organizational objectives and to explore new areas of interest in VLSI domain while being resourceful, innovation and flexible.

CORE COMPETENCY:

Programming Languages: C, C++, and Verilog & System Verilog.

Basic Knowledge: Digital design concepts, CMOS fundamentals, ASIC Design flow, Physical Design & layout design Concepts, STA, Network analysis, Analog design Fundamentals, AHB & I2C protocols.

EDA Tools Experience:

Place & Route: IC Compiler(Synopsys)

Physical Verification: IC Validator(Synopsys), Calibre(Mentor Graphics)

Static Time Analysis: Primetime(Synopsys)

Extraction Tool: Star RC(Synopsys)

Technology: 180nm

EDUCATION:

6 months Advanced Diploma in ASIC Design from RV-VLSI Design Center, Bangalore.

M.Tech (signal processing and VLSI Design) from SBMJCE Bangalore (Jain University) with Aggregate of 84.45%.

B.E. (Electronics and Communication Engineering) from BLDEA’s CET Bijapur (VTU Belgaum) with aggregate of 71%.

12th from RMG Jr. College Mudhol (Karnataka State Board of Education) with 84%.

10th from Navodaya school (Karnataka State Board of Secondary & Higher Secondary Education) with 82.88%

PROJECT:

Ethernet packet loopback design verification using System Verilog

Description: Design checks the incoming Ethernet packets at the receive interface for CRC, sof errors, data Len errors, etc. Packet is looped back on Transmit interface if it is good, else dropped. As part of this design verification we developed test bench with generate all types of Ethernet packets and also developed reference model for the self-checking the design behavior.

Tools used: Questasim

Responsibilities: Listing down features, scenarios

Test plan development

Developing test bench architecture

Coding Test bench components including reference model and checkers

Verification closure using Functional coverage & code coverage as closing criteria.

Block Level Implementation of a SOC-Subsystem.

Description:

Torpedo is a subsystem with 6 main IP cores

Technology: 180nm

No. of macros: 32

Clock Frequency: 400 MHz

Area:5.9mm2

Supply Voltage: 1.8V

No. metal layers: 6

Power Budget: 300 mW

Foundry : Jazz Semiconductor

Responsibilities:

Deciding congestion free Floor-plan with high Macro count

Fixing the power planning based on IR-Drop & EM analysis

Worked on timing driven-placement, analysis of timing path, timing report, fixing setup, and hold and slew violation and skew optimization.

Timing closure with aggressive timing constraints

Clock Tree Synthesis meeting specified targets

Routing & optimization.

Physical verification (DRC, LVS, ANT)

Fixing Pre and Post layout STA

Memory Controller Functional Verification using Verilog.

Description: Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. It has support for 8 chip selects. It also supports flexible timing configuration for different memory types. As part of this design verification, we created test bench using SV to generate scenarios targeting all types of supported memories for different possible combinations & different sizes supported. We also developed monitor, reference model & checker as part self-checking test bench implementation.

Tools used: Modelsim

Responsibilities:

Listing down features, scenarios

Test plan development

Developing test bench architecture

Coding Test bench components including reference model and checkers

Verification closure using Functional coverage & code coverage as closing criteria.

PERSONAL DETAILS:

oDOB: May 7th 1990

oNationality: Indian

oMarital Status: Single

oGender : Female



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