Curriculum vitae

CHAITHANYA B.S

BINDU SREE, MRA C7,

Mangalassery Lane, Email Id: c actfbz@r.postjobfree.com, Pappanamcode P.O c actfbz@r.postjobfree.com

Trivandrum, Kerala,

India, Postal code: 695018 Contact No: +919********* CAREER OBJECTIVE:

To gain a dynamic and challenging role in the area of ASIC Verification where performance is rewarded with new responsibilities utilizing my knowledge and skills and providing growth opportunities and exposure that contribute to organization's as well as individual development.

Summary of Qualifications

Good understanding of the ASIC flow

Experience in writing Test benches in SystemVerilog as well as in SystemC

Work Experience in Verification Methodologies such as UVM

Strong knowledge in AMBA AHB and APB protocols

Developed Verification Environment Infrastructure and Functional tests

Experienced in Constrained Random, Coverage driven and Assertion based Verification

Worked on Functional as well as Code Coverage

Experience in using Questasim/Modelsim, NCSim,ISE, Keil and Encounter RC Compiler Key Achievements

Published the paper “Assertion Based Reconfigurable Testbenches for Efficient Verification and Better Reusability” in IEEE Conference held at Karpagam College of Engineering, Coimbatore

Published the paper “Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness & Reusability” presented at Design & Reuse Conference, Grenoble, France

Technical Skills

HDL VHDL, Verilog

HVL SystemVerilog, SystemC

Scripting Language TcL/Tk

Operating Systems Windows,Linux

Protocols AMBA AHB,APB, Ethernet,UART

EDA Tools Questasim/Modelsim, NCSim, Xilinx ISE, Keil, Encounter RC Compiler Knowledge UVM/OVM,RTL coding, FSM Based Design,Simulation, Synthesis Others C/C++, 8051 programming, MATLAB, HTML & PHP Experience & Employment History:

Present Job Title &

Employer :

Electronic Design Engineer

Magic Array Technology Solutions

Kazhakuttom, Thiruvananthapuram, Kerala, India

Previous Job Title &

Employer :

Project Engineer I

Centre for Development of Advanced Computing

(Ministry of Information & Technologies, Govt. of India) Thiruvananthapuram, Kerala, India

Experience 2.5 years of Industrial Experience

Education

Master of Technology in VLSI and Embedded Systems from Cochin University of Science and Technology (CUSAT), India with a CGPA of 8.89 in 2014

Bachelor of Technology in Electronics and Communication Engineering from University of Kerala, India with a CGPA of 8.33 in 2012

12t h

Class from St. Thomas Central School, affiliated to CBSE board, with an aggregate of 82% in 2008

10t h

Class from St. Thomas Central School, affiliated to CBSE board, with an aggregate of 90.3% in 2006

Major Assignments:

1. Verification IP for SDRAM Controller and AMBA Advanced High Performance Bus o Developed the Verification Plan

o Modelled UVM based Advanced High Performance Bus (AHB) protocol in System Verilog

o Modelled UVM based Advanced Peripheral Bus (APB) in System Verilog o Implemented Assertion based and Coverage driven Verification o Developed Constrained Random stimuli for the Verification o Introduced Self Checking Mechanism

o Developed Design document and Project related Documents 2. Verification IP for GPIO Controller and Real Time Clock o Developed the Verification Plan

o Modelled Advanced Peripheral Bus (APB) in SystemC o Developed Constrained Random stimuli for the Verification o Developed all direct and random testcases

o Introduced Self Checking Mechanism

o Created the verification environment in SystemC

o Developed Design document and Project related Documents 3. Verification Environment for UART & Ethernet

o Developed the Verification Plan

o Modelled UVM based Advanced Peripheral Bus (APB) and General Purpose Processor in System Verilog

o Identified and developed testcases to verify the basic functionality o Implemented Assertion based and Coverage driven Verification o Developed Constrained Random stimuli for the Verification o Created Verification Environment Components using UVM Personal Profile

Age & Date of Birth : 25 years, 28 11 1990

Sex : Female

Marital Status : Married

Hobbies & Interest : Reading, listening to music, Solving SUDOKU, cooking, jewellery making Personal Traits : Optimistic and a major team player with the ability to bring out the best in everyone

Declaration:

The information provided above is true to the best of my knowledge and belief. TRIVANDRUM CHAITHANYA BS

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