Nagella venkatesh

Email Id: acteu7@r.postjobfree.com, phone No:855*******.

Objective:

To obtain a position where I can enhance my skills and contribute to the company. Academics:

Degree

Institute/University Year of passing Percentage/CGPA M-Tech(VLSI) VIT University,

Vellore, Tamilnadu.

2015

8.7

B-Tech(ECE) Vidya jyothi institute of

Technology (JNTUH),

Hyderabad,

Andhra Pradesh.

2012

70.71

Intermediate Gowtham junior college,

Vijayawada,

Andhra Pradesh.

2008

92.6

SSC Montessori High School,

Alampur, Mahaboob nagar,

Andhra Pradesh.

2006

90.16

Technical Skills:

scripting languages : Perl.

Functional Simulation : Questa Sim, Spartan3(Xilinx), nclaunch (Cadence) .

Synthesis Tools : RTL Compiler (Cadence), Quartus II (ALTERA).

Physical Design : Cadence SoC encounter, Cadence Virtuoso (Full Custom Design and Layout design).

Hardware languages : Verilog HDL, system Verilog, UVM .

Familiar with ASIC Design flow, STA and FPGA implementation.

MATLAB

Software Languages : Basics of c, Data structures, object oriented program(oops). Experience :

During my training period from july 22 2015 to Jan 22nd, 2016 in Maven silicon training institute, I have done verification projects like

i) RAM RTL design and verification using system Verilog and UVM methodology. ii) Router 1x3 protocol RTL design and verification using UVM methodology. iii) UART IP core verification using UVM methodology. iv) AMBA AHB protocol RTL design and verification. Projects :

Design of Router 1x3 protocol and its verification using UVM Methodology. Tool used: Questa sim and Riverapro.

Description: In this Router 1x3 means Router contains one input source and three destination output channels. The input source will forward the data packets to any one of the destination output channel based on the address. Before sending packets to destination channels, data packets are stored in FIFO’S. I have written RTL code for router based on input and output protocol and verified using UVM methodology.

M-tech projects:

1. Implementation of reduced hardware encoding and decoding of Reed Solomon error correction codes its verification and physical design.

Tool used: Cadence (nclaunch, RTL compiler, SOC Encounter), Model sim, FPGA DE2-115 board. Description: In this project, reduced hardware encoding and decoding of Reed Solomon error correction codes using constant multipliers has been implemented and also parallel decoder is proposed that corrects more errors at a time. Physical design has been designed for parallel decoder. 2. Design of RNS based multistage programmable decimation filter and its physical design. Tool used: Cadence (nclaunch, RTL compiler, SOC Encounter), Model sim. Description: This paper presents a decimation filter for multi-standards like WCDMA and WLAN which finds application in today’s communication. The architecture is described in Verilog and logically synthesized in 180nm standard cell library with cadence design compiler. 3.Design and implementation of 16-bit RISC processor. Tool used: Cadence (nclaunch, RTL compiler), Model sim. Description: In this work, an 16 bit RISC processor is presented with higher performance. This processor comprises of program counter, Instruction memory, Instruction decode unit, general purpose registers, Arithmetic and logical unit.

4. Delay Analysis and Design of a Low-Voltage, Low-Power Double-Tail Comparator and its Layout.

Tool used: Cadence Virtuoso tool.

Description: In this project, we have described the analysis on the delay of the dynamic comparators are compared and a new double tail dynamic comparator is proposed for low-power and fast operation of ADC(Analog to digital converters) at small supply voltages. . Areas of interest:

Digital IC design, RTL design and Verification.

Analog IC design.

ASIC Design.

Co-curricular activities and Achievements:

Participated in "VLSI system verification using system verilog" organised by VLSI Division, School of Electronics Engineering, VIT University, in the year 2014.

Qualified Gate(graduate aptitude test in engineering) in the year 2013.

Got state 7th rank in PGECET in the year 2012.

Achieved 1st prize in coco game conducted in Montessori high school in the year 2008.

Achieved 2nd prize in Hindi essay writing competition conducted in Montessori high school in the year 2003.

Personal traits:

Hobbies: Playing chess, Swimming.

Strength: Hardworking, Motivating myself, Self-confidence. Personal Details:

Name

Nagella Venkatesh

Father’s Name N.Veerabhadrappa

Gender Male

Nationality Indian

Date of Birth 14-07-1991

Languages Known Telugu, English, Kannada.

Marital Status Single

Permanent Address H.NO: 5-97B, chowdeshwari temple street, kodumur, Kurnool(Dis), Andhra Pradesh, pin:518464.

DECLARATION

I do hereby declare that all the information mentioned above is true to the best of my knowledge and belief.

Place: Bangalore

Date: 05-02-2016 (Nagella venkatesh)

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