Raval Jay Manoj

M.Tech. (VLSI Design)

*/* **** *****, *********** gate, Marathahalli, Banglore-560037 Contact No: +91-942**-*****, 822**-*****

Email: actedl@r.postjobfree.com

Career Objective:

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible. Basic Academic Credentials:

Qualification Board / University Year of passing Percentage / CGPA M.Tech.

(VLSI Design)

Vellore Institute of Technology,

VIT University

Pursuing (2016) 8.22

B.E. (ECE)

Universal College of Engineering,

Gujarat- Technological University

2013 7.83

H.S.C.

Diwan Ballubhai School Ahmedabad,

Gujarat board

2009 72.00%

S.S.C.

Diwan Ballubhai School Ahmedabad,

Gujarat board

2007 87.08%

Internship:

Project Title ASIC Implementation of channel equalization technique for LTE (Long term Evolution) Organization name Project Trainee at DRDO (Advanced numerical research and analysis group-ANURAG) Project duration July 2015 to till now

Description

In this project implementation of LTE standard modules like LMS adaptive filter, Pipelined adaptive filters, CRC-16 code generator, Scramblers and Descrambler have been designed and verified. ASIC/FPGA implementations have been done during this project. Tools Used Xilinx design ISE 14.3 (Virtex7-XC7VXC330T), Cadence RC launch (TSMC-180nm). Project Title Physical design of CEWA-32 bit Processor. Description In this project starting from floor planning, preplaced cell location, power planning, placement, clock tree synthesis, timing analysis, routing, DRC clean, parasitic extraction i.e. physical design flow have been implemented.

Tools Used Cadence SOC Encounter.

Projects PG level:

Project Title

Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm.

Description

In this project 2 parallel, 3 parallel and 4 parallel FIR filter implementation are done by using Fast FIR Algorithm. By using proposed method of symmetric convolution based on Fast FIR Algorithm, implementation of 2 parallel transposed direct form FIR filter is done. FPGA & ASIC based implementation are done during this project. Tools Used Xilinx design ISE 14.3 (Spartan 3E-XC3S100E), Cadence RC launch (TSMC-180nm). Project Title Layout implementation of 16-bit ripple carry adder. Description

In this project schematic and layout of 16-bit ripple carry adder is implemented and layout is verified by DRC and LVS. Interconnect resistance and capacitance is calculated by using RC extraction.

Tools Used Cadence Virtuoso Layout Suite XL.

Project Title Structural adders’ reduction in fixed coefficient transposed direct form FIR filters. Description

In this project a new method of structural addition for the fixed coefficient have proposed. By using that method trying to reduce the area and power of fixed coefficient transposed Direct form FIR filter. FPGA & ASIC based implementation are done during this project. Tools Used Xilinx design ISE 14.3 (Spartan 3E-XC3S100E), Cadence RC launch (TSMC-180nm). Project Title ASIC implementation of 8-bit Adding-CPU processor design. Description

In this project implementation involving arithmetic, data path and control path instruction in verilog code and performing functional verification, timing analysis and carried out RTL to GDS-II physical design flow by using Cadence Encounter. Tools Used Cadence NC launch, Cadence RC launch, Cadence SOC Encounter. Project Title Low power 6-T SRAM cell design.

Description

In this project different low power technique likes SRAM memory banking, derived word line, derived bit line have been implemented.

Tools Used Cadence Virtuoso.

Project UG level:

Project Title RF based wireless speed control of DC motor for various applications. Organization name “Embelink” Automation India Private Limited Project duration July-2012 to May-2013.

Description

This is project based on industrial defined problem. In this project there are two section remote section and control section. From the remote section trying to control the speed of DC motor by using RF based wireless system. In this project solution is given to industry for fully automated system where number DC motors are used for various applications. PIC18lf4520 Microcontrollers, RFM22B Transceivers, 16*2 LCD display, LM317 power supply, 12V DC motors etc and MP Lab.

Research Paper Publications:

Published the paper titled “Structural adders’ reduction in fixed coefficient transposed direct form FIR filters” in International Journal of Engineering and Technical Research (IJETR), ISSN: 2321-0869, Volume-3, Issue-2, and February 2015.

Technical Skills:

Languages / Scripting Verilog HDL, Basic of PERL and TCL scripting. Hardware Tools / Utilities

Cadence Encounter, Cadence Virtuoso, Model-Sim, Xilinx design ISE 14.3, Cadence RC launch, Cadence NC launch, MP Lab, Lab-View, Matlab. Operating Systems Windows, Linux – Ubantu

Area of Interest:

Digital IC design, Low power IC design, ASIC & FPGA based design. Personal Details:

Father’s name : Raval Manoj Rasiklal

Date of Birth : 14/11/1991

Marital status : Single

Sex : Male

Nationality : Indian

Languages Known : English, Hindi and Gujarati

Hobbies : Chess, Cricket

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Extra Curricular Activities & Achievements:

Attended state level seminar on “Microcontroller and Embedded C Programming” at Nirma University.

Represented as a University level Chess player at state level competitions.

Attended state level seminar on “Lab view - Used in VLSI testing” at VIT University.

Achieved second rank in college during first year and achieved third rank in college during UG. Declaration:

I hereby declare that the above given information and details are true to the best of my knowledge. Date: Place:

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