NOKIB UDDIN

****, *** ** *’Epee, Montreal, QC H*N 2C9 Ph. 514-***-**** Email: act754@r.postjobfree.com; act754@r.postjobfree.com Professional Summary

Focused Candidate with broad-based background in highly competitive and dynamic organizations, Recognized as a leader and excellent team player. Professional, hands-on, hardworking, highly motivated, mature, organized, positive, multi-task oriented, responsible

Profile

3 year experience on ASIC and FPGA design, High Speed Digital Design and digital logic design and Verification, RTL synthesis and embedded system and IC development.

2 year experience on Formal Verification, Formal Methods, Model Based Development, Model Checking.

Strong knowledge of programming in C/C++, Matlab and software structures.

Hand of experience in hardware description language (VHDL, Verilog) and high level Verification language (System Verilog).

Experienced with Cyclone FPGAs, Xillinx Spartans and Xillinx Spartan 3 and 7 Series FPGAs.

Hand of experience in Temporal logics (LTL, CTL, CTL*, TCTL), LTS, TLOTOS.

Experienced in using tool sets; such as Xillinx ISE design suite, Vivado, Verriloger Pro.

Experienced with Communicating Sequential process (CSP), Traces, Failures, FDI model, Modeling of Embedded and Real time systems.

Proficiency in using lab equipment including pattern generator, logic analyzer, oscilloscope. Education

MSc in Concentration Computer Science Sep.13 – Jul.15 Bishop’s University, Sherbrooke, QC

MSc thesis: Formal Methods, Formal Verification & Model Based Development Computation tree logic (CTL) is equivalent to failure trace testing Course Works: Model Based Testing of Reactive Systems, Concurrent & Real Time Systems, Communicating Sequential Process (CSP), Model Checking, Automata Theory and Computational Complexity and. BSc in Electronics & Communication Engineering Feb.08 – Jul.12 Khulna University of Engineering & Technology, Khulna, Bangladesh BSc thesis: FPGA based Microprocessor design

FPGA based Sigma delta modulator design for biomedical application using Verilog HDL Course Works: Digital Electronics, Power Electronics, VLSI Design, Microprocessor & Micro Computers, Computer Networks, Data Structure, Advanced Computer Programming, Information Technology, Communication Systems, Antenna Engineering, Micro waves & Fields. Courses/Training:

Architecture Wizard and I/O Planning (Xilinx)

FPFA vs. ASIC Design Flow (Xilinx)

Work Experience

Verification Specialist Aug.15 to present

Atos SE, Montreal, QC

• Designing Car Simulation Model using Vector Canoe 7.6.

• Analyzing DTC signal using SM Trace and Canoe.

• Running and analyzing test cases and test functionality, usability and performing regression testing that spans across the radio and telematics software including integrations with mobile devices.

• Also able to increase the testing efficiency 20%. Graduate Research Assistant Sep.14 – June 15

Bishop’s University, Sherbrooke, QC

Worked on Parallel and Real-Time Research Group (PART). We approached on formal methods, testing and systems. Our main drive was in formal methods and formal verification. Another direction in our research was thus the study of algebraic, compositional approaches to this area.

Proved that Model Checking (CTL) and Model based (Failure Trace testing) testing is equivalent.

Provide an algorithmic solution that allows the free mix of logic and algebraic specifications for any system, thus offering increased flexibility and convenience in system specification for formal verification. Internship Jun. 14 – Aug. 14

Sargent Aerospace & Defense, Anjou, QC

Worked on Automation and Continuous Improvement Engineering project. The work was related with automated manufacturing process and need to maintain complex systems embodying electronics and electro- mechanical principles of aircraft systems production.

Fixed a problem in the automatic manufacturing process, which increased the products quality 10%.

Figured out the way to generate problem report (section wise and specific reason) form the automatic generated production report.

LinkedIn: https://ca.linkedin.com/pub/nokib-uddin/31/7b5/796

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