Design Project

Amey Telang ************@*****.***,

+60-103******, 999-***-**** ************@*****.***

EXPERIENCE SUMMARY:

VLSI Front End Design professional having a consolidated experience of around 7+ years with more than 2 years of team leading experience and 6 years of technical experience in RTL Design & Application functions.

Have worked with Global (Multinational) customer centric organizations like Larsen & Toubro, Lattice Semiconductor Corp. & eInfoChips.

Technical Exposure:

Digital logic Design

Micro-Architecture Design

RTL coding using Verilog and VHDL

Good experience on FPGA and CPLD Designs with exposure to ASIC Designs

IP Integration and Testing

Reverse Engineering Projects & Exposure to Avionics Domain

Synthesis and P&R (FPGA, CPLD’s)

Timing Analysis (FPGA’s) & Chip Level Debugging

Functional and Timing Simulation with Test Bench

High Speed Design, SERDES Applications and Silicon Level Issue Debugging

Protocol knowledge on OTL, 10GMAC Ethernet, ARNIC 429, AURORA, AXI-64, AXI Lite, APB Bus

Board Design and Debugging Using DSO, LA, DMM, FG.

Tool Exposure

Synopsys (Synplify Pro), Lattice Diamond

XILINX ISE & VIVADO

ALTERA QUARTUS

Modelsim, Isim, QuestaSim, Active-HDL

Orcad, Eagle Schematic Design

PADS Layout PCB Review & HyperLynx SI Analysis

Process Management Exposure

DO-254 Processes

AS-9100 Procedure

SVN, CVS

L-1 & B1/B2 USA VISA.

PROFESSIONAL RECOGNIZATION AND ACCOLDES

Rewarded Core Value Award for Managing 6 Projects Team in Parallel.

Rewarded with Pat on Back Award for Handling Trainings to Fresher and AS9100 Audits.

Rewarded for handling more than 120 customers outside India in a Quarter.

Rewarded for creating more than 70 FAQ’s and 30 CR’s in a Quarter.

Rewarded for creating a Utility for Programming and Configuration of ECP3 devices.

PROFESSIONAL DEVELOPMENT

Hexosys Bhd (Kuala-Lumpur, Malaysia) Feb’16 – Till Date

Sr. Design Engineer – (Research & Development)

eInfochips Ltd. (Ahmedabad) Feb’14 – Jan’16

Technical Lead – (ASIC Division)

Lattice Semiconductor International Corporation (Bangalore) Sep’12 – Jan’14

Sr. Design & Application Engineer – (FPGA, Reference Design & Core IP)

Larsen & Toubro (Integrated Engineering Services, Mumbai) Feb’08 – Aug’12

Design Engineer – FPGA & VLSI Front End Projects – (Electrical Automation)

Key Accountabilities (Individual Contributor)

PROJECT 1 : Optical Channel Transport Lane Design (IP Design) {External- Germany}

Implementation of OTL layer @ 40Gbps (4X10Gbps) for Optical Transport Network as per the OTU3k standard definition which includes different levels of design implementation for Clock Deskew, Frame Detection, Frame Alignment and De-skewing, Lane Rotation Detection and maintains, Lane De-skewing. The Design also validated by using GTX Trans-receiver of Kintex-7. Below are the parts of my job:-

a)RS, FS, HLD, DLD Creation & Freezing

b)Micro-Architecture Design of System with RTL Design using Verilog

c)Integration of Transmitter and Receiver

d)Support to Verification team for IP Verification Environment bring up & 100% Code Coverage.

e)Complete Board Level Validation using GTX Trans-receiver of Kintex-7

f)Integration using AURORA protocol

g)Timing Analysis for 156.25 MHz.

h)8b/10b decoding, 64b/66b decoding usage & SFP Module integration using SERDES

i)Test Bench Creation for Module and Top Level

j)Schematic design using Orcad, 8 Layer PCB design review using PADS & SI Analysis using HyperLynx.

PROJECT 2 : Demo Design of OTL to 10G MAC Ethernet (Verilog, Kintex-7)

This project focuses over the implementation of demo for OTL and 10G MAC Ethernet integration. The project involves complete understanding of OTL and Ethernet protocol and respective IP’s individual working. The integration involves the challenge of maintaining a 10G to 40G speed & vice-versa along with the multiple protocol understanding and respective calculations. Below are the parts of my job:-

a)System Architecture design Creation & Freezing

b)Micro-Architecture Design of System with RTL Design

c)Integration of OTL Transmitter and Receiver with 10G MAC Transmitter and Receiver and PHY.

d)Design of AXI-64 and AXI-Lite FSM for 10G MAC initialization and transmission and reception.

e)XGMII to GMII and Vice-Versa block design for PHY interface.

f)Test Bench Creation for Top Level testing

g)Timing Analysis for 156.25 MHz. & 10MHz.

h)Complete Board Level Validation

PROJECT 3 : SatLinkMAX_avPM & ARINC-429 IP design

Client : External- USA

RTL Used : VHDL

FPGA Targeted : Cyclone IV

The project has to different phases. First scopes to create the required documentation following SOI-1 through SOI-4 Job Aids for the successful DO-254 DAL-C Level certification of product used for real time Satellite-based voice and data communications and second scopes to the designing of ARINC-429 generic IP & its validation over Cyclone IV.

a)Gap analysis List of Artifacts for the DO-254 DAL-C certification & standard.

b)Plan for COTS Components, PHAC, V & V, HCMP, HPAP, ECMP Creation

c)SOI-1 through SOI-4 Job Aids and DO-254 Objective Mapping for each phase

d)ARNIC 429 protocol understanding and IP architecture and Functional Design to support 12.5 & 100 KHz.

e)Micro-Architecture Design of ARNIC-429 with RTL Design using VHDL Guidelines

i)Test Bench Creation for Top Level testing

j)Timing Analysis for 1 MHz.

f)Complete Board Level Validation

Key Accountabilities (Technical Lead)

PROJECT 1 : 6 FPGA Design Migration and Validation (Onsite-USA)

RTL & FPGA Used : Mixed (VHDL + Verilog) & Spartan 6, MAX10

The project pertains to migration of Automatic Electrical Test Equipment RTL designs to Xilinx Spartan 6 and Altera MAX 10 device. My role pertains to technically guide on the below mentioned task and managing a team of 8 engineers working in parallel on this project. Duties also involved in Project Proposal creation, Client Call Management, Weekly Status Reports and Presentations, Resource Management, Handling of Sales Calls, Project Schedule Design and Management.

PROJECT 2 : APB-SPI Master & I2C Slave IP Design

RTL & FPGA Used : VHDL & Kintex-7

The project pertains to specification, architecture and micro-architecture design of APB-SPI IP and I2C Slave IP design. This involves guiding to juniors over SPI and I2C protocol and APB bus protocol along with mentoring them over design flow and challenges with complete design, verification and validation environment creation and guidance over RTL design, Synthesis, Timing analysis & P&R.

PROJECT 3 : UFS HCI

RTL Used : Verilog

My Role : The project requires ASIC prototyping on targeted Virtex-7 and Zynq-7 FPGA using VIVADO and ISE. The first task involved detailed Timing Analysis which needs to be performed along with its failure resolution against 190MHz. targeted frequency. Second, it required long memory splitting task used in ASIC design for Low Power consumption. The task involves continuous coordination with Verification Team against any RTL modifications. Finally, a code needs to be modified as per Ladda and Spyglass reports along with following Verilog Coding Guidelines.

Silicon Level Issues Debugged: Dual ECP3 Silicon Programming Issue, XP2 PLL Phase Issue, ECP3 100MHz. PLL Issue, ISPMACH4000 Burnt IO Issues, iCE40 SPI and I2C Location Issue, JTAG Cable Power Issue, Timing Issues

Devices Interfaced: SFP, LCD 16*2, RS232 Port, HEXKEYPAD, SRAM, DC MOTOR, STEEPER MOTOR, VGA PORT, PWM SYSTEM, PS-2

ACADEMIA

Post Graduate Diploma in VLSI DESIGN (2007-2008) from Semi-Conductor Laboratory (Vedant Institute), Chandigarh, India.

Bachelor of Engineering (B.E.), in Electronics & Communication (2003-2007) from Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal, India.

Date of Birth : 21/05/1986

Languages Known : English, Hindi, and Marathi

I affirm that the above information is true to the best of my knowledge.

Date: Amey Telang

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