E-mail : ********.*****@*****.*** Website : in.linkedin.com/in/kalrav18
Phone : 760******* Address : C/14,BHAKTINAGAR SOCIETY, NEAR SURYADEEP TOWER,
GURUKUL ROAD, MEMNAGAR,
AHMADABAD, GUJARAT - 380052
PGD in Vlsi And Embedded Hardware
Technology
August-2014 Feb-2015
Electronics And Communication May-2011 May-2014
Electronics And Communication May-2008 May-2011
SSC May-2007 May-2008
KALRAV JOSHI
Personal Summary
Highly motivated to work in a reputed rapidly growing VLSI Hardware Design company with a dynamic Environment that provides learning, early responsibility and a productive work culture along with effectively contributing towards the goals of the organization.
Technical Skills
physical design (cadance)
verilog/vhdl (modelsim, cadance)
embedded-c & Assembely (keil)
fpga & psoc (xilinx)
orcade
Education
National Institute Of Electronics And Information Technology passed with B+ grade
Gandhinagar Institute Of Technology
Passed with 6.59 CGPA
Vpmp Polytechnic
Passed with 6.98 cgpa
Vishwabharti High School
passed with 70%
KALRAV JOSHI 1
Project
NIELIT
RISC USING MIPS: Here we tried to overcome disadvantages of RISC architecture by MIPS technology.here we have introduce hardware which is 16 bit wide & supports multiplication as well as division instructions.as well as we have introduced pip-lining stages (single cycle) & tried to over come data hazard & control hazard using stall & flush instead of branch-prediction logic.after completing the front-end part we have done complete physical layout (GDSII File) using cadence tool.
SECURITY ACCESS CONTROL SYESTEM: Here we had introduced the basic security access control system with some features like GSM modem 3 layer securities. here if user enter wrong password more than 3 times then the gsm modem through message 'll send the appropriate authority & if the password match with the default one then the user can access the an object. We have interface keyboard, 16x2LCD display, buzzer, relay & GSM modem. Here we are using simple micro processor & coding done by our-self in keil.we have generate also simulation & pcb layout using ORCADE.
RTL VERIFICATION OF FIFO AND 1024X8 RAM: Verification of the given RTL of a FIFO by using some test benches and different test case scenarios thereby automate the program and correct the errors. G.I.T
GSM BASED ELECTRONICS NOTICE BOARD: this project is the very advantageous in now a days. it reduce boring paper works. so to be helpful to my Gujarat Technological University we have done this project. Here whatever the circular or message regarding to College University members send through via message & it will automatically display on the display board. so all can read easily . This is project is combination of embedded and communication. Vpmp
AUTOMATIC TEMPRETURE CONTROL SYESTM: here we had introduced very fantastic automatic industrial application. Here slave device is connected with GSM modem & send automatically temperature of particular area & accordingly master take action through GSM network only. This project is the combination of pure electronics & communication.
Publication
RISC USING MIPS TECHNOLOGY IN “INTERNATIONAL JOURNAL FOR REASERCH AND DEVELOPMENT IN TECHNOLOGY”- VOLUME-3 /ISSUE-4 (APRIL-2015)
Extra Curricular Activity
•NCC CDT (‘B’ Grade in “C”-Certificate)
•Member of rifle club and Gujarat vidyapith snanagar
•Runner up of XENESIS 2013
•Attended IEEE Workshop of VLSI DESIGN SYSTEM in 2013
•Attended conference about INTERNET OF THINGS in 2014 Language Competencies
HINDI
ENGLISH
GUJARATI
KALRAV JOSHI 2
References
• Nandakumar.R, Scientist C, Coordinator (All India VLSI And Embedded Hardware Design), NIELIT, Calicut. Ph: +919*********
• Gautam Varma - Broadcom, Bangalore ph: 906-***-**** KALRAV JOSHI 3