Hardik Trivedi

M.S (VLSI Design)

Email : act1nd@r.postjobfree.com

Mobile : +91-982-***-****

Profile Summary

Currently Working as Technical Associate (ASIC Verification) at E-Infochips Training and Research Academy Ahmedabad.

Master in VLSI Design and experience in ASIC Verification Domain.

In-depth knowledge on ASIC Verification with Verilog and System Verilog.

Excellent communication and presentation skills.

Self-motivated, Responsible, Ability to adapt and willingness to learn. Professional Experience:

Organization: E-Infochips Training and Research Academy, Ahmedabad. Duration : July 2015 to till date

Designation : Technical Associate

Description:

Team Member in E-ITRA Live Projects i.e USB 3.0, AMBA APB Bridge Peripherals.

Framing labs according to E-Infochips requirement

To Train graduates and professionals in ASIC Verification Domain. Project Details:

Current Projects:

VIP development of AMBA-APB Slave:

I have developed AMBA-APB slave environment in which the whole verification Environment with Layer Test bench Architecture with different component like Packet class, driver, monitor scoreboard etc. Developed Assertions and coverage for the same. With the randomization along with re-usability and oops concepts successfully developed an Environment in System Verilog in VCS tool.

Develop VIP of USB 3.0 SuperSpeed Physical Layer:

The project aimed at to manage transfer data either on 2.5 GT/s or 5.0 GT/s depends upon the mode and rate. In Design I manage to capture the data that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data.

Verify the complete design of USB 3.0 SuperSpeed Physical Layer using System Verilog. I wrote an exhaustive verification plan from the specifications. I created Verification Environment in System Verilog.

Develop VIP of USB 3.0 Link Layer (LTSSM):

Verification of LTSSM state machine of USB 3.0 using System Verilog. Link Training and Status State Machine (LTSSM) is a state machine defined for link connectivity and the link power management. Designing is done in Verilog and simulation is done in Cadence tool. Verification is done in System Verilog using CRV (Constrained Random Verification) methodology.

M-Tech Project:

HDLC CONTROLLER DESIGN:

Designed HDLC transmitter using Verilog HDL, HDLC protocol was implemented with transmission of 8bit flag, followed by data transmission by synchronous FIFO which was further processed by zero stuffing in order to differentiate data from flag bit during reception. HDLC Receiver received data bit by bit. Reception begins with recognition of flag register, which indicates the reception of new HDLC frame, followed by zero unstuffing process, and after that data is received by secondary station.

Academic Profile

Master in Science (VLSI Design)

Manipal University

CGPA 8.43

2012 – 2014

Bachelor of Technology (Electronics & communication) Rajasthan Technical University

58.31 %

2007-2011

HSC 71.20 %

SSC 72 %

Technical Skills:

Programming C, C++

Scripting PERL, Shell

HDLs & HVLs Verilog, System Verilog

Methodology UVM

Protocol USB 3.0 (Physical Layer, Link Layer), HDLC, AMBA APB Tools Synopsys VCS, Cadence NCSim, ModelSim 10.2, QuestaSim 10.2b, DVE, Icarus Verilog OS Linux Red Hat, Linux CentOS 7

Certification:

SOC Verification using System Verilog by Udemy.

Achievements:

Secured Runners-up position in Inter Collegiate Volleyball Tournament in Feb 13-14.

Played State Level Volleyball Tournament in 2010.

Secured 4

th

position in National Level Youth Parliament in 2006. Paper Represented:

Published paper on “Design and Verification of USB 3.0 Link Layer (LTSSM)” at International Journal of Computer Science and Information Technologies (IJCSIT), Vol. 5 (4), 2014, 4916-4921

Published paper on “Implementation of USB 3.0 Super Speed Physical Layer Using Verilog HDL” at International Journal of Computer Applications (IJCA) 95(24):1-5. Published by Foundation of Computer Science, New York, USA

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