VLSI Design & Verification RTL Engineer

Pradap k

Email-Id : acsz7t@r.postjobfree.com

Contact no. : +91-880*-***-***

OBJECTIVE:

Seeking a job in VLSI - RTL Design (SoC / IP level) to continue & enhance my career as a VLSI Engineer DESIGN SKILLS:

Architecture – IP & SoC level

ARM based SoC

Micro-architecture

Verilog HDL design

SoC Integration

Debugging

Synthesize ( Xilinx & Quartus)

Assertion for design

EXPERIENCED PROTOCOLS / IP:

VinRZ5110 RISC processor (Equivalent to ARM966E)

AMBA – AHB

VinSMDP / IDT - Debug & Trace tool for VinRZ5110 processor

AES – Advanced Encryption Standard

DMA controller

UART – Universal Asynchronous Receiver Transmitter ADDITIONAL SKILLS:

Unix commands

Tools – CVS (Concurrent Version Control), Questasim, Quartus, Modelsim & Xilinx WORK EXPERIENCES:

Working as VLSI Design & Verification Engineer – at Vinchip systems pvt. Ltd., Chennai, from August 2012 to till date

One year work experience as Electronics research associate at Dextrasys technologies pvt ltd., Trichy EDUCATIONAL QUALIFICATION:

Completed Bachelor of Engineering (B.E) in ‘Electronics and Communication’ at M.I.E.T Engineering College with the percentage of 78 in Trichy

Scored 87% in HSC and 86% in SSLC

PROJECT DETAILS:

PROJECT – 1 : AMBA-AHB

Responsibility : Design, Verification – Simulation, Synthesize & FPGA Validation Design : Designed the AMBA AHB protocol, which can support maximum number of masters

& SPLIT & RETRY capable of slaves & integrated with VinRZ5110. Contributed in the design phases such as partitioning, micro-architecture, pseudo code & implementation (IP and SoC level) Validation : Synthesized by using Quartus – II & validated by using Altera – stratix FPGA Team size : 5

Duration : 1 Year (2012 - 13)

PROJECT – 2 : VinSMDP / IDT

Client : DRDO - CABS, Bangalore

Responsibility : Design, Verification & Synthesize Design : Designed VinSMDP / IDT, that is a non-intrusive memory debugging & trace capture tool for VinRZ5110. Especially we have added acknowledgement for all input commands from GUI Validation : Synthesized by using Quartus – II & validated by using Altera – stratix FPGA Team size : 5

Duration : 8 months (2013)

PROJECT – 3 : AES

Responsibility : Design, Verification – Simulation, Synthesize & FPGA Validation Design : Designed AES (Advanced Encryption Standard) which can support 128,192 & 256 bit keys for encryption and decryption. Matrix algorithms & calculations are the real challenge in this project Validation : Synthesized in both Xilinx 13.1 & Quartus – II Team size : 3

Duration : 9 months (2013 - 14)

PROJECT – 4 : VinRZ DMA

Responsibility : Design, Verification – Simulation, Synthesize & FPGA validation Design : Designed a DMA, which is compatible with AMBA AHB. This Soc have DMA, AHB & UART are major blocks. The DMA consists of modules such as controller, configuration, FIFO (size: 512 word), memory controller Validation : Synthesized by using Quartus – II & validated by using Altera – stratix FPGA Team size : 3

Duration : 1 Year (2014 - 15)

Address : S/o. Karuppaiah A, 23/15f - Veerampatty, Velur-(post), Viralimalai-(via), Pudukkottai - (Dt) – 621 316, Tamil Nadu, INDIA

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