Vlsi engineer, rtl verification,system verilog, ar experienced level

SHIVANI YADAV

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M.TECH (VLSI) with Exposure in Designing, Verification and Digital Domain at Experienced level

OBJECTIVE

To pursue a challenging career in leading and progressive research organization offering opportunities for utilizing my skills towards the growth of the organization.

PROFESSIONAL EXXPERIENCE

Worked at SOFCON INDIA Pvt. Ltd Noida, as a VLSI Verification Engineer from September 2014 to October 2015.

PROJECTS UNDERTAKEN

DESIGN AND ANALYSIS OF LOW POWER SRAM ON CADENCE VIRTOUSO TOOL

Design a Static Random Access Memories (SRAMs), focusing on optimizing delay and power. Cell is being modified such that it is used as a latch type sense amplifier to amplify and store the small swing write data presented on the bit-lines which reduces power and delay factor.

IMPLEMENTATION OF 8B/10B ENCODER/DECODER OF GIGABIT ETHERNET FRAME

It is hardware as well as on software(VERILOG) based project. The encoder on the transmitter side maps the 8-bit parallel data input to 10-bit output on behalf of serializer and deserizlizer concept the data stream will be transmitted through transmission media to the receiver where decoder decodes the data stream and give desired outputs while maintain all errors, DC balanced.

VERIFICATION OF A 5 STAGE PIPELINED LC3 MICROCONTOLLER.

Designed a layered and object oriented verification test-bench to identify the bugs in a RISC 5-stage, pipelined LC3 microcontroller. Constrained random testing were used. This project was executed using System Verilog in QuestaSim.

DESIGN AND VERIFICATION OF AMBA APB ADDER USING VHDL.

Design & Verification of an APB Adder (32-bits) acts as an APB Slave and takes sixteen clock cycles to perform addition using VHDL. APB version 2.0 protocol is followed. The design is synthesized on Quartus II Web Edition and is simulated/verified using ModelSim.

ACADEMIC QUALIFICATION

M.Tech in VLSI Domain from Amity University, Noida, UP in the year 2012-14 having 9.08 CGPA.

B.Tech in ECE from GBTU in the year of 2007-11 with 71.94%.

HSC from St. Xavier’s senior sec school, CBSE board in the year of 2007 secured 73% marks

SSC from S.D Public school CBSE board in the year of 2005 secured 82% marks

TECHNICAL PROFICIENCY

Hardware Description Languages: VHDL, Verilog and System Verilog.

Expertise in Digital Design and Advanced Verification Techniques.

Worked on RTL Verification level, simulation and synthesis using Xilinx ISE, XST tools.

Good understanding of timing analysis of circuits at gate level and on analog CMOS concepts.

Tools: Mentor graphics tool, HDL designer’s tool, proficient in Cadence Virtuoso. Learned Modelsim, Questasim for simulation and Quartus II, Simplify for synthesis, Linux, FPGA, XILINX ISE design suite, MATLAB.

PUBLICATION

Published in Thapar University’s Conference ICECIT-13 with paper titled “LEAKAGE POWER OPTIMISATION USING LECTOR TECHNIQUE”.

Research Paper titled “LOW POWER SRAM DESIGN WITH REDUCED READ/WRITE TIME” in the International conference on "Advancements in computing sciences, information techniques & emerging e-learning technologies" (ACSITEET– 2013)to be held at Jawaharlal Nehru University, ISSN 0974-2239, Volume 3, Number 3, 2013.

Published in IEEE conference WECON 2014 at Andhra Pradesh with paper titled “IMPLEMENTATION OF 8B/10B ENCODER/DECODER OF GIGABIT ETHERNET FRAME”.

INTERNSHIP

1.Title: Design & Verification of an AMBA APB Adder

Company: CVC Pvt. Ltd. Bangalore

Duration: 6Th May to 31st June’13

Software: QUARTUS II

2.Title: Implementation of 8B/10B encoder decoder of Ethernet frame on SPARTAN 6

Company: CDOT Delhi

Duration: 6th December13 to 17thMay14

Software: QUARTUS II, Xilinx ISE design suite

AWARDS AND ACHIEVEMENTS

Got Merit Certificate for highest academic performance in the 2012-13 session at Amity University Noida.

Attended the workshop Reliability Engineering Technologies by Prof.Shui, Nanyang Technological University, Singapore at Amity University.

Attended the Mobile Technology Conference MECON’10 organized at Amity University Noida.

Attended the workshop on Nanofabrication technology INUP’13 organized by ISC Bangalore.

Joint academic lecture workshop on history, aspects and prospects of electronics in India, organized by Delhi University, New Delhi, 2012.

Certificate of appreciation from student and youth welfare society.

Certificate of appreciation from the Deputy Commissioner of Police Traffic.

Participating in technical project exhibition.

PERSONAL DETAILS

Date of Birth : 21st September 1989

Nationality : Indian

Sex : Female

Language Known: Hindi and English and Knowledge of French.

SHIVANI YADAV

Place: Delhi

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