Project Design

RUSHIN VILESHBHAI PATEL

B.Tech. (Electronics & Communication)

ADDRESS : */******* ***** *******, ******** of Vishwanagar Flates, Nadiad- 387001. E-MAIL ID : *************@*****.***

PHONE NO. : +91-955*******

DOB : 27/09/1993

CAREER OBJECTIVE:

To work with a world-class organization where I will get the chance to learn new skills and make use of my existing skills to perform for the betterment of the company,where I can prove myself . ACADEMIC DETAILS:

Course

Year of Passing

Percentage

SPI

University/

Board

Faculty

of

Technology,

Dharamsinh

Desai

University.

B. Tech.

(E.C.)

Semester- 1 DEC-2011 72.50% 8.00

Semester- 2 JUN-2012 70.10% 7.76

Semester- 3 DEC-2012 78.00% 8.55

Semester- 4 APR-2013 81.80% 8.93

Semester- 5 NOV-2013 80.80% 8.83

Semester- 6 APR-2014 74.40% 8.19

Semester- 7 NOV-2014 78.30% 8.58

Semester- 8 APR-2015 82.50% 9.00

Average SPI:-8.63

H.S.C

2011

86.15%

New English Day

School, Dakor Road,Opp of Sai Baba

Temple Nadiad-387001

GHSEB

S.S.C

2009

87.85%

St Annes High School,

District Court

Road,Nadiad-387001

GSEB

TECHNICAL SKILLS:

Projects Accomplished:

TRAFFIC LIGHT CONTROLLER (5th Sem) : In this project I make a traffic signal light Using digital logic gates, 555 timer and counter, here the traffic signal light automatically get Change after fixed amount of time from one light signal to another light signal.

EFFECTIVE CAR PARKING (6th Sem) :In this project, I make one car parking which Having LCD display at entrance of the parking which shows that which slot of parking is empty in the parking so that we can directly go to that slot and park our car without wasting our time and petrol, this project I designed using 89c51 microcontroller.

SMART ARRAY ANTENNA (7th Sem) : In this project, I designed one smart array antenna designed using MATLAB software, this is basically pure software project. First I reduces SIDE LOBE LEVEL up to minimum level than I moved the direction of maxima into desired user direction for getting maximum signal into desired direction.

EVENT BASED TRIGGER AND CLOCK GENERATOR FOR TIMING SYSTEM(8th sem): In this project, I designed one timing system which will provide necessary clock frequencies to data acquisition system according to event generated at input side of timing system. For this we are using FPGA(XC3S500E) Xilinx board to design various digital components modules that are useful to divide the frequency as well as to select particular frequency among all frequencies.

CHIPTOP (PHYSICAL DESIGN PROJECT at Eitra) : During my six months of training at Eitra (E-infochips institute of training and research) in Physical Design I did this project in which I took the synthesis netlist and place and route that design along with the clock and signal routing. At the end of project I tried to solve various timing problems related to project. As a backend engineer I need to resolve certain problem related to design that are Setup and Hold violations .

Areas of Interest:

VLSI - Physical Design

Basic Electronics

Application Specific Scripting

Computing Skills:

Software Tools :- Scilab, Matlab, Keil, Quartus, ISE design suite for FPGA programming (Xilinx) and LabVIEW for ARDUINO .

From Synopsys :- DC(design compiler) for Synthesis, ICC for PNR, PT(Prime Time) for STA.

Assembly Language Programming(8051,8086),C/C++,Verilog Programming,PERL Scripting language, Linux Shell Scripting, AWK programming, TCL programming. LANGUAGES KNOWN :

English, Hindi & Gujarati

INDUSTRIAL VISIT AND EXTERNAL TRAINING :

Wanakbori Thermal Power Station

At Eitra (E-infochips Institute of Training and Research Academy) for 6 months in Physical Design. NON TECHNICAL ACHIEVEMENTS:

Kheda District Cricket Player for last 6 years ( University Cricket Team Captain for 1 Year).

IEEE Student Branch Representative for 1 Year.

Active Member of Spandan (Social Service Group). HOBBIES:

Listening Songs

Playing Cricket

Dancing ( On a loud music)

REFRENCES:

NAME POST CONTACT DETAIL

Dr. Nikhil J. Kothari

Professor & Head, Department of

Electronics & Communication,

Faculty Of Technology, D. D.

University, Nadiad- 387001

Telephone : (026*-*******

Email Id : ***********@***.**.**

Prof. Narendra .V. Chauhan

Assistant Professor, Department

Of Electronics & Communication,

Faculty Of Technology, D. D.

University,

Mobile : +91-989*******

Email Id : ***.**@***.**.**

DECLARATION:

I hereby declare that the above mentioned information is correct up to my Knowledge and bear the responsibility.

( Rushin Patel )

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