LAVANYA K G
ASIC design verification trainee
CVC PVT LTD, BANGALORE
Email id: email@example.com
Mobile. No: 994-***-****
A keen Strategist in design & verification of VLSI circuits, leveraging a strong background in electronics. Looking for a responsible position as an ASIC Design Verification Engineer with a view to utilize and enhance my skills and experience towards professional growth.
Simulation Tools : Modelsim 10.0d, Questasim 10.2c, VCS, Cadence (NCsim), Riviera- Pro v.2013.10
Synthesis Tools : Xilinx ISE 14.1, Altera Quartus II 12.1
Hardware Description Languages: Verilog, VHDL
Hardware Verification Language: System Verilog
Software Skills: C, C++
Verification Methodologies: UVM 1.1c
Platforms: Windows, UNIX
Scripting Languages: Perl, TCL
Protocols and Standards: AMBA -APB 3.0
Application software: MS Office (Word, Power Point, Excel)
RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, Digital Design, VLSI Digital Signal Processing Systems, ASIC & FPGA Flow, System on Chip (SoC), CFV (Comprehensive Functional Verification)
oASIC DESIGN VERIFICATION TRAINEE, CVC PVT LTD
oM.E.(VLSI Design) from K S Rangasamy college of Technology, Tiruchengode in 2013-2015 with CGPA of 8.18
oB.E.(Electronics and communication Engg.,) from Adhiyamaan College of Engineering, Hosur in 2009-2013 with CGPA of 8.58
o12th from Maharishi Vidhya Mandir Higher Secondary School, Hosur with 66.56%
o10th from Maharishi Vidhya Mandir senior Secondary School, Hosur with 75.35%
oPaper published in International Conference on Intelligent Information Technologies (ICIIT) on DETECTION AND CLASSIFICATION OF FEATURES IN FUNDUS IMAGES OF DIABETIC PATIENTS – A REVIEW held at Anna University.
oPublished the paper in an International Journal for Applied Engineering and Research (IJAER) on SEGMENTATION OF ANATOMICAL STRUCTURES IN RETINAL IMAGES (Annexure – II).
oPublished the paper in an International Journal for Engineering Research and Technology (IJERT) on AN INTELLIGENT ENVIRONMENTAL NOVELTY SYSTEM USING MOBILE TECHNOLOGY FOR WARFIELDS., Vol.2 - Issue 10 (October - 2013), 2278-0181.
oStudied and implemented a mini project on ‘Obstacle Detecting Robot’ and ‘Surveillance Robot’.
oTitle: An Intelligent Tactical treaded Robot Using Mobile Technology’
oDomain: embedded system
oDescription: This project focusses on the usage of robots in defense that serves to reduce human loss. It was designed with many features like movement, obstacle detection and wireless camera for motion capturing. These features are essential in defense that uses all possible technologies to monitor and control at border areas.
oTools used: Embedded C and Proteus
oTitle: VLSI Implementation in Segmentation and Classification of Retinal Images
oDescription: The retinal analysis is essential in case of patients affected by diabetic retinopathy. The images are trained for both normal and abnormalities. All possible set of abnormalities are trained and on the basis of the features extracted for optic disc, the images are classified. These are widely used in easy interpretation of images and its data. These were further implemented in VLSI using System generator software.
oTools Used: MATLAB and SYSTEM GENERATOR
TITLE: Designing of AMBA 3 APB Protocol
The APB3 is part of the AMBA 3 protocol family. It provides a low cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface.
Developed design using Verilog.
Developed System Verilog verification environment.
Developed System Verilog Assertions.
Environment: System Verilog, Rivera pro
Team Size: 1
oStrong oral and written communication
oProblem solving skills
oWell-developed research skills
oTime management skills
Name : LAVANYA K G
Date of Birth : 05/04/1992
Father’s Name : Mr.K.R.Govindarajulu
Nationality : Indian
Address : 4/317-A1, 3rd Cross, Moovender Nagar
Bagalur Road, Hosur – 635109
Tamil Nadu, India.