Engineer Project

Curriculum Vitae

Narendra Solanki

Address:

H*02, Golden Star

Bangalore 560048

India

Phone (M): +91-994*******

Mail: *******.**@*****.***

Total Experience: 19 years

VLSI: 14 years

Skill Summary

Strong in Advance Functional Verification Methodology – eRM, OVMe, OVM, UVM

Strong in Coverage Driven Verification(CDV) solution like Specman

Reg Mem Modeling using VR AD, UVM REG

In-depth knowledge of PCI Express Protocol

Strong in Metric Driven Verification(MDV) methodology using vManager,vPlan

Exposure to SoC and HW-SW Co-verification using ISX

Executed complex Projects and Programs successfully

Exposure to Project Management

Deployment of various protocol Cadence VIPs, Denali Purespec VIPs

Paper Publication to Forums like CDNLive, ToT

Good communication skills

Experience summary (starting with the latest)

1.From 2014 YBN Infrateq Pvt Ltd. as Director.

2.From 2012 to 2014 Ericsson, Sweden as ASIC Designer responsible for function verification of one of the most complex ASIC Designs

3.From 2005 to 2012 with Cadence Design Systems currently designated as Sales Tech Lead AE working with various accounts for deployment of Coverage Driven Verification Methodology, Metric Driven Verification Methodology, VIP Development, Closure Automation SysTem using Cadence Tools.

4.From 2004 to 2005 with CMR Design Automation Pvt. Ltd as Senior CE. Worked with various accounts supporting deployment of Coverage Driven Verification Methodology, Metric Driven Verification Methodology, VIP development

5.From 2000 to 2004 with e-Infochips Pvt. Ltd as Verification Engineer. Worked for Designing Filters, developed eVCs and supported customers.

6.From 1994 to 2000 with Aston Electronics for Designing and Troubleshooting of Digital Analog, Embedded Control System

Professional Experience

Ericsson, Sweden: 12/2012-06/2014

Role: ASIC Verification Engineer

Responsible for designing Verification Test Bench using Specman’s eRM methodology and managing project with Metric Driven Verification Methodology to verify one of the cutting edge most complex ASIC Designs for Digital parts of Product Line Base Stations HW Product Portfolio. Exposed to Lean Product Development methodology for efficient project management. Developed eVC to verify in-house memory interfaces.

Cadence Design Systems: 6/2005 – 12/2012

Role: Tech Lead Application Engineer

Deployment of eRM, Coverage Driven Methodology, Metric Driven Methodology, System Verification Methodology, HW/SW Co-Verification Methodology, Advance Verification Management with using Specman, vManager, ISX, VIPs, PureSpec PCIE Denali VIP, OVM/UVM, CAST (Closure Automation SysTem) at various clients’ base like TI, NXP, Infineon, Samsung, Rambus, HCL, STMicro, Conexant, Intel, LSI, KPIT, TataElexsi, Wipro, MindTree, Sasken etc

Project: PCI-Express Root Complex, End Point Verification with Rambus

Worked with GDA Tech Engineer to integrate RTL with PCIe VIP to verify RC and EP configuration using Metric Driven Methodology using vPlan and vManager.

Paper Co-Authored:

CDNLive 2007: PCI Express Design IP and Verification IP integration

Project: Re-Use of Verification Environment for Verification of Memory Controller for

NXP Semiconductors India Pvt. Ltd

http://www.design-reuse.com/articles/18329/verification-memory-controller.html

Methodology adopted to address the re-use of the test environment/testbench at unit level across testing of highly abstract level models (modeled in SystemC) and RTL models (modeled in VHDL/Verilog)

Methodology and challenges faced towards unit level verification of complex TLM (SystemC) model (memory controllers: external static memory controller and external nand flash controller) using this re-use methodology

Methodology in creating verification IP's to provide interfaces to enable its re-use at these different levels of abstraction

Following tools are used in this methodology:

Specman Elite as the functional verification tool which supports coverage driven verification methodology

vManager for plan driven verification

Scenario builder to create specific scenarios.

eVCs as the verification IP's

Project: PowerPC based SOC verification, Defense Govt of India

Role: Team Lead

Lead a team to verify PowerPC based SOC using Specman based eRM and SVM methodology. Also used Metric Driven Methodology using vPlan and vManager to drive closure of the verification task.

Project: GFX Verification, OVMe Pilot Project DSPS, Texas Instruments

Developed GFX (Graphics) eVC from scratch using OVMe methodology for Display Sub System (DSPS). Verified GFX DUT with MDV methodology using vManager and vPlanning.

Project: HVL Driven Execution Sequencer (HDES), Texas Instruments

Challenges were to mitigate verification issues in HW/SW Co-verification like Verifying Software in correlation with RTL, UVC regeneration with C test cases, Case based function calling, Reusing Functional verification setup for Palladium setup, Interface with Hardware box Palladium platform for higher throughput etc

Deployment of ISX helped addressing these challenges on HW-SW co-verification.

Presented Paper “HVL Driven Execution Sequencer (HDES)”Co-Authored for CDNLive 2011

CMR Design Automation Pvt. Ltd, Bangalore: 10/2004- 6/2005

(Distributor for Verisity tools)

Role: Senior CE

Customer Support: Verification Environment Development

Developed various VEs, VIPs for verifying DUT’s like Multi Media Card, Digital PLL,RISC

Processor using Verisity’s industry standard eRM methodology using 'e' verification

language and Specman tool for clients like TI,Wipro

Customer Support: Verification with vManager

vManager is the industry’s first solution that automates the management of complex

verification projects and guides verification from planning and goal setting, to closure.

Worked with Clients like Intel, Agere, Wipro for verifying SOCs s using vManager flow

starting from vPlan creation, environment setup, regression run, failure analysis and

reactive measures as per analysis.

Customer Support: Training

Conducted training sessions for customers on Specman Basic, eRM and Advanced

Specman training.

e-Infochips Pvt. Ltd, Ahemedabad:12/2000-10/2004

PCI Express eVC (e Verification Component) Development/Verification:

PCI Express eVC is used for functional verification of IP cores and SoC designs incorporating the PCI Express Link capabilities. PCI Express is a third generation I/O interconnects that will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms.

Involved in developing verification environment for verification of the PCI Express eVC. Worked extensively in verifying PCI-Express eVC non eRM and eRM compliance core utilizing Coverage Driven Verification (CDV) methodology. Involved actively for verification environment and test suit development.

Used Specman Elite's e-language extensively for writing test cases, checks and developing sequence library. Future computing and communications platforms.

Worked as a key team member for architecture definition of Physical layer. Also extensively

worked for developing Non eRM Physical layer incorporating complex logic for LTSSM

state, Transmitter block, Scrambler, De-Scrambler modules. Involved actively for initial

architectural development, Core development for Phy layer.

Customer Support on PCI-Express eVC:

Profoundly involved in first line of support to various clients. My responsibilities were to generate bug condition, validating bug resolution and providing effective solution/package to client. Extensively used remote logins, Webex to excel support across the globe. Also successfully maintained GNAT Bug Tracking System (BTS) for logging clients' RFEs and Defects.

On Site Verification of PCI-Express RTL DUT: Philips, Tempe Arizona, USA

Successful training for two weeks to Philips team on PCI Express protocol and eVC architecture.

Involved in imparting training on PCI-Express protocol and PCI-Express eVC.

Integrated and setup an environment for PCI-Express Root Complex DUT using PCI Express eVC for client.

Developed semi-random and random test scenario generation using eVC for the DUT verification. Found various bugs in first integration of eVC itself.

Tools: Specman Elite, Verilog-XL, FinSim, ModelSim

Languages: e-Language, Verilog

Platform: Solaris, WindowsNT, Linux

Generic FIR filter

FPGA design flow starting from functional spec, design spec, RTL design, Pre-Synthesis Simulation, Post Synthesis Simulation.

Physical Verification of the Core using extensive features of MATLAB.

Preparation for documents and deliverables for Xilinx's Alliance Core partnership program.

Tools: ModelSim, Ambit, Xilinx Foundation series, Matlab

Languages: Verilog, Perl

Platform: Windows NT4.0, Unix -Solaris

41-tap R-Cosine FIR Filter for Client

R-Cosine filter is used to filter side-band signals to reduce power consumption load on

Transmitter. Responsible for single handedly designing 41-tap R-Cosine FIR Filter.

Involved in Post Synthesis Simulation of the core.

Tools: ModelSim, Leonardo Spectrum, Xilinx Foundation Series, Matlab

Languages: Verilog

Platform: Windows NT4.0

ITU-T Recommendation G.168 Digital Network Echo Canceller

Acted as important member of the verification team, Verified Non Linear Processor of Echo

Canceller using test vectors and reference model developed in MATLAB.

Generated test vectors for ITU-T G.171 test conditions.

On-board Verification of Echo Canceller Core with ITU-T G.171 test conditions.

Synthesis of Echo Canceller Core on Ambit and Xilinx with constraints.

Tools: ModelSim, Leonardo Spectrum, Ambit, Xilinx Foundation series, Matlab

Languages: Verilog, Perl

Platform: Windows NT4.0, Solaris

ASIC flow methodology with BLAST CHIP

Offshore project for Magma-DA Inc., USA:

Extensive Hands-on-Training on Magma Blast Series of RTL-To-Silicon Tools covering...

Logical effort, Library qualification process and Fixed Time methodology.

Static timing analysis, Floor planning, Place and Route process.

Comparative study of SDC (Prime Time) and Magma (Mantle) Constraints Formats.

Extensive scripting in TCL-TK covering various constraints of pilot project.

Worked on pilot project of echo canceller to implement the design from RTL to GDSII .

Tools: Blast Chip (Magma)

Languages: TCL/TK, M-TCL

Platform: Linux and Solaris

Calorex Institute Of Technology, Ahmedabad: 6/2000-11/2000

Intel MCS 51 compatible micro controller

Involved in all phases of the project like functional specs, Design specs, RTL coding, verification.

RTL development and synthesis: Developed the ALU module for CPU.

Tools: ModelSim, and Leonardo Spectrum

Languages: Verilog, Perl

Platform: Windows NT4.0

Other Industrial experience, Mumbai & Ahmedabad: 6/1994-11/2000

Design and Troubleshooting of Digital Systems

Profoundly worked on Diagnosis and debugging of shooting relay based punch type time record machines.

Completely involved in the diagnosis of digital circuits and smooth working of the automatic plant.

Actively involved on system integration, installation and commissioning of PC systems and Medium size LAN networks.

Completely responsible for the diagnosis of automatic time record machines.

oEducation Qualification:

B.E (Electronics & Communication), 1993, S.D.M College of Engg. and Technology, Dharwar, Karnataka

Qualifications

Verification Languages: “e”

Hardware Languages: Verilog

Verification tools used: Specman,eManager,ISX

Hardware Simulator: IUS

Operating Systems: Windows, Linux

Papers Co- Authored to various forums :

CDNLive 2007 - PCI Express Design IP and Verification IP integration

CDN Live 2008 - Verification Improvement using CDV and TLM 2.0

CDNLive 2011 - HVL Driven Execution Sequencer (HDES)

www.design-reuse.com : Re-Use of Verification Environment for Verification of Memory Controller

http://www.design-reuse.com/articles/18329/verification-memory-controller.html

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