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Engineering Test Cases

Location:
Hyderabad, Telangana, India
Posted:
December 23, 2015

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Resume:

M.UDAY KIRAN Mobile: +91-849*******

*-***/*, **/*, Anand Nagar Colony, +91-868*******

Bandlaguda, Rajendranagar E-Mail:acsv33@r.postjobfree.com Hyderabad-500086 acsv33@r.postjobfree.com

OBJECTIVE

To become a genuine technologist by working in a technically challenging environment and to deliver my capabilities that would contribute to the growth of the organization as well as my career growth in all respects.

EDUCATIONAL PROFILE

Discipline Institution Board/

University

Year of

Passing

Aggregate/

Percentage

M.TECH

(Integrated circuit

Technology)

Hyderabad central

university(HCU)

Central

university

2016

8.61(CGPA)

till 2nd sem

B.E (Electronics

and

Communication

Engineering)

Vasavi college of engineering

Osmania

University,

Hyderabad

2013

76.9

12th Class

Intermediate

Narayana junior college

Board of

Intermediate

2009

95.1

Secondary

School

Certificate

Brilliant grammar high school

SSC

2007

91.6

SOFTWARE SKILLSET

Languages : C, C++, Oracle10g, MatLab and UNIX

EDA tools : Mentor Graphics, Xilinx ISE, Silvaco, ADS.

HDL & HVL : Verilog, System Verilog

Packages : MS Office 2007

ASIC Design Tools : Xilinx, Modelsim.

Domain : ASIC/FPGA front-end Design and Fabrication layout. AREA OF INTEREST

VLSI (RTL Design and Verification), FPGA Prototyping, Digital Signal Processing, IC Design and fabrication.

ACADEMIC ACCOMPLISHMENTS

Presented paper on biomedical applications of “NANOTECHNOLOGY” in PEARL- 2012 organized by BITS Hyderabad.

Participated in a “ROBOTIC WORKSHOP” organized by Vasavi Engineering College, Hyderabad as a part of Acumen.

Attended analog design workshop conducted by Austria Microsystems (AMS) at Vasavi college of engineering.

Fabricated a GaAs Mesfet in clean room as part of M.Tech course. PROJECT WORK (CURRICULAR)

“Biometric based Electronic voting machine using fingerprint sensor with 8051 microcontroller while pursuing a Degree in Electronics and Communication Engineering.

Hardware tools used: Microcontroller(8051),LCD,RS232 Serial Communication, Keypad, Finger Print sensor.

Software tools used: KEIL IDE (Compiler, Assembler, Debugger, Editor,Simulator).

Languages: Embedded C

EXPERIENCE

Worked as Software Engineer in IGATE global solutions and got hands on experience in UNIX as part of my project.

CURRENT ACTIVITIES

Completed 1st year M.Tech in Integrated Circuit Technology and looking ahead for an opportunity to enter into the VLSI domain.

PROGRAMS ATTENDED

Pursued Higher Education Program (HEP) on design verification using System Verilog offered by Mentor Graphics during my vacation period of 45days.

Underwent hands on training in concepts of System Verilog language for creating Verification Environment using Mentor graphics Tools QuestaSim10.4 and concepts of UVM Methodology for Design Verification.

Worked on mini projects to develop the System Verilog test bench environment and generate random test cases for Verification.

MINI PROJECT WORK [VERFICATION OF LC3 MICROCONTROLLER] 1. BUG ANALYSIS OF VERIFICATION ENVIRONMENT

HVL: System Verilog TOOL USED: QuestaSim 10.4

DESCRIPTION AND RESPONSIBILITIES: For a given LC3 microcontroller verification environment, applied System Verilog concepts and developed a bug report by checking the functionality against the given specifications. 2. MODULE LEVEL VERIFICATION OF PIPELINE

HVL: System Verilog

DESCRIPTION AND RESPONSIBILITIES: Developed the module level verification for each pipeline stages of the microcontroller using the SV concepts and verified the functionality as per the specification.

3. DEVELOPMENT OF TEST SCENARIOS

HVL: System Verilog

DESCRIPTION AND RESPONSIBILITIES: Created the Environment around DUT and developed random test cases to verify different scenarios as per the verification strategy.

4. FUNCTION COVERAGE CLOSURE

HVL: System Verilog

DESCRIPTION AND RESPONSIBILITIES: Collected the Module level Functional coverage numbers for each and every block of the LC3 microcontroller to generate the functional coverage report and collected the whole coverage numbers for Verification Sign off.

PERSONAL PROFILE

Name : M.Uday Kiran

Date of Birth : 29-Aug-1991

Marital Status : Single

Permanent Address : 7-236/a, 13/a, Anand Nagar Colony, Bandlaguda, Rajendranagar

Hyderabad-500086

Languages Known : English, Telugu, Hindi.

I hereby declare that the particulars furnished above are true to the best of my knowledge. Place: Hyderabad

Date : 2/12/15 M.UDAY KIRAN



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