M.Tceh

CIRRICULUM VITAE

Email id:acsv2z@r.postjobfree.com

Ph no:703-***-****

To work in a healthy, innovative and challenging environment extracting the best out of me, which is conducive to learn and grow at professional as well as personal level thereby directing my future endeavours as an asset to the organization.

.

Degree

College/School

Board/University

Year Of Passing

Percentage

M. Tech Specialization

in VLSI

Koneru Lakshmaiah Education Foundation.

KL UNIVERSITY

2016

8.96CGPA

(up to I-1)

B. Tech Specialization

in ECE

Tenali Engineering College,Anumarlapudi.

JNTU, Kakinada

2014

72

Intermediate

JLB Junior College For Girls, Rpalle.

Board of Intermediate Education

2010

64.9

S.S.C

ZPHigh School,Kolakaluru.

Board Of Secondary Education

2008

61

Programming Languages : C,VHDL &Verilog

Simulation Soft wares :MATLAB,Xilinx,Cadence,DSCH2&MICROWIND

Working knowledge of Microsoft word, Power point, Excel.

Actively taken part in Organizing College Symposiums.

Title : Main Project on “Industrial Process Control And Automation Using Zigbee Technology”.

Description : The basic purpose of this project about the design and development of industrial process control and automation using ZIGBEE technology.

S.NO

SOFTWARE TOOL USED

PROJECT TITLE

1.

XILINX

DESIGN AND IMPLEMENTATIONS OF 5X7 DOT MATRIX.

2.

DSCH2 & MICROWIND

DESIGN AND IMPLEMENTATION OF

CARRY LOOK A HEAD ADDER.

3.

CADENCE ANALOG

1) STUDY AND COMPARISION OF 2 PHASE ADIABATIC SWITCHING LOGIC

2)DESIGN AND IMPLEMENTATONS OF ILBERT CELL

TITLE: VARIABLE INPUT DELAY CMOS LOGIC FOR LOW POWER DESIGN

Description: In this paper we are reducing the power dissipation by using static and dynamic power dissipations. The CMOS logic circuits we are giving the input producing the output at some delay so we are getting the glitches. The reducing the glitches in order to reducing the power dissipation and increasing the speed of operation of the CMOS circuits .

Participated in paper presentation.

Participated in poster presentation.

Participated in poster presentation.

Comprehensive problem solving abilities and analytical skills.

Hard working.

Good verbal and written communication skills.

Team building abilities.

Adaptability to situation, confidence and optimism.

Playing games.

Gardening.

Listening music.

Name : Kolakaluri.Spandana

Date of Birth : 10-05-1993

Gender : Female

Father Name : Mr. K.Nageswara Rao

Languages Known : English, Telugu

Nationality : Indian

Address : H-NO:6-91

Gudivada(post), Tenali(M.D),

Guntur(DIST), Pin Code-522307.

I am confident that I shall strive and succeed in the position applied to the satisfaction of my superiors and justice the assignments entrusted on me. I declare that the information furnished above is true to the best of my knowledge.

Place: Gudivada

Date: 02/7/2015

Name of the Candidate

(K.Spandana)

Contact this candidate