Engineer Technical Support

DAVID A. SIMS

San Diego, Ca. *****

(Home – 858-***-****, Cell – 858-***-****)

Email: ***********@*****.***

https://www.linkedin.com/pub/david-sims/14/475/a38

BACKGROUND SUMMARY

I am a results driven, Senior EDA Product Applications Engineer, with emphasis in FPGA technology. I have many years of professional work experience, serving as an individual contributor, as well as organizing and managing my own FPGA technical support group. I am a seasoned, customer facing, support specialist with a unique talent for rapidly learning new technologies, tools, and methods for betterment of the organization and customer’s I serve.

I have a broad background of experience and skill sets in the following areas:

- Sustaining existing customers and providing technical support for issues in the field before, during, and after production.

- Uncovering revenue opportunities, demand creation, project management, developing user application notes, demos, training, benchmarking, complex issue resolution, and strategic planning.

- Working with third party EDA tool vendors to manage software releases and licensing.

- Knowledge of FPGA partitioning and prototyping debug for SoC.

- Strong background in the areas of FPGA front-end synthesis, digital design, HDL coding, RTL optimization/debug, place and route, timing analysis, and design automation.

- Knowledge of OVM/UVM, TLM, and SystemVerilog test bench verification.

- Trusted advisor and knowledge expert, for any organization seeking a customer facing, technical expert on their products.

SKILLS AND KNOWLEDGE

HDL Languages: Verilog, VHDL.

Programming/Scripting Languages: C, TCL, Perl, assembly language.

Operating Systems: UNIX, Linux, Windows.

Support: Customer trainings, demos, issue resolution follow-up, root cause analysis. Debug/Synthesis/Simulation/Emulation/Timing Analysis EDA tools: Protolink Probe Visualizer, Synplify Pro, Verdi, Siloti, VCS, Altera Quartus II, Xilinx: (ISE, Vivado), Modelsim, Zebu Server 3.

Lab Skills: Debugging multi-FPGA, SoC prototyping boards with software debuggers and oscilloscopes.

Version Control: ClearCase, CVS.

Protocols: PCIe, USB, DDR, UART, AMBA, SATA/SAS.

Other Skills/Knowledge: Transactor based co-emulation/simulation acceleration, C++, C#, Python, SystemVerilog Testbench, UVM/OVM, FPGA partitioning and prototyping for SoC, SerDes, 100 Gigabit Ethernet, RTL debug, static timing analysis (STA), timing closure, place and route, HSPICE, DRC/LVS, FEC, schematic capture, schematic reviews, PCB layout, embedded programming, Matlab, Simulink, Agile, Scrum.

PROFESSIONAL EXPERIENCE

Springsoft/Synopsys – San Diego, Ca.

March/2012 – August/2015

Field Applications Engineer

Dedicated FAE to Qualcomm supporting the Synopsys Protolink Probe Visualizer verification tool for debugging custom, multi-board/multi-FPGA HW prototyping systems, for early, design cycle bring-up of the SoC RTL. My accomplishments included the following:

Utilizing Protolink, I enabled Qualcomm’s emulation engineers to verify correct partitioning of their latest SoC RTL, and at the same time cut their RTL development cycle in half.

Optimized, deployed, and promoted new and more time efficient debug methodologies at Qualcomm, to differentiate the capabilities of Protolink, from competing RTL debug solutions.

Successfully implemented Protolink to debug 4 major chip tape outs for Qualcomm. From this success, I helped secure a multi-million dollar deal to permanently include Protolink debug methodology, in their latest SoC emulation flow.

Scripted and tested transactor based co-emulation flows, using the Synopsys VCS simulator and transactor IP, enabling a 20% increase in simulation speed over Qualcomm’s competing, co-emulation solution.

Arrow Electronics - Englewood, Co.

September/2008 -November/2011

FPGA Applications Engineer

Dedicated Altera FPGA Applications Engineer supporting all Arrow FAEs and customers designing with Altera devices and software. My primary responsibilities included the following:

Successfully created, managed, and served in Arrow’s first, in-house support center called ATAC (Altera Technical Assistance Center) comprised of five engineers, dedicated to handling Altera pre and post-sales technical support issues.

Through ATAC, I increased the overall bandwidth of Altera’s, native support group by 30%, and provided more comprehensive technical support, to both Arrow’s direct customers and FAEs.

Debugged the full range of FPGA design issues such as RTL coding/synthesis, timing closure, place and route, IP integration, external memory, embedded processor, device programming, and systems level, high-speed, IO interfaces.

Performed requested design conversions from Xilinx to Altera compatible logic for Arrow FAEs to help win 20% new business engagements for my assigned territory.

Altera - San Diego, Ca.

October/2004 – September/2008

Senior FPGA Applications Engineer

Senior Applications Support Engineer in the Altera NARSC (North American Regional Support Center) based in San Diego, for customers and FAEs using the Altera Quartus II FPGA design software tools and devices. My primary responsibilities included:

Optimized customer’s source VHDL and Verilog RTL code for synthesis, place and route, timing closure, better utilization of the device architecture, and performance criteria.

Provided technical support, demos, and training on all issues related to Altera Quartus II design software, for all North American customers and FAEs.

Developed new solutions collateral, such as FAQs and user application notes, for resolution of customer issues, reducing Quartus II software tickets by 25%.

ADDITIONAL RELEVANT EXPERIENCE

ASIC Applications Engineer, Nurlogic Design/Artisan Components (now part of ARM), San Diego, Ca.

FPGA Applications Engineer (ORCA line of FPGAs), Lucent Technologies, Allentown, Pa.

Hardware Design Engineer/ASIC Engineer, Motorola, Huntsville, Al.

EDUCATION

Bachelor of Science, Electrical Engineering – Clemson University

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