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Power Plant Training

Location:
Suri, WB, India
Posted:
December 20, 2015

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Resume:

CURRICULAM VITAE

Specialization : (VLSI Design)

AMRITA KUMARI

Mob :- 955-***-****

Dwarka Sector-8, New Delhi

Email:- acsu3i@r.postjobfree.com

Objective

To excel through creative ideas and smart work and attain a respected position in an organization with growth opportunity in Electronics & Telecommunication and take a challenge in the field of VLSI.

Educational Qualification

M.Tech (VLSI) - Sharda University, Greater Noida, UP - (2015) - 7.6 CGPA

B.Tech (Electronics & Communication Engg.) MIT,Purnea - (2012) - 79.80%

Intermediate (I.sc) - Purnea College Purnea (2005) - 61.40%

High School - BSEC, Patna - (2003) - 69.60%

Technical Skills

Field of interest: Verilog/ System Verilog/ Digital Electronics.

HDL: Verilog.

HVL: System Verilog.

Methodology: UVM.

Other Languages: Linux/ Shell/ Perl/ C-Language/ Little bit of German.

EDA Tools : Working on XILINX/ Modelsim/ Questasim/ NC Sim/ Cadence Encounter/ FPGA/ OR-CAD/ Microwind/ DSCH .

M.Tech Projects:-

1. “ AMBA Based AHB Lite Protocol ”

The main component types of an AHB-Lite system are Master, Slaves, Decoder, Multiplexer.

Simulation on QuestaSim and Synthesis on Xilinx ISE and implementation on Spartan 3E FPGA (Xilinx).

2. Working on verification environment of ( Generator, Driver, DUT, Monitor,Scoreboard, /Mailbox) of FIFO, ALU and RAM Memory using System Verilog.

B.Tech Projects:-

1.“Implementation Of 16-bit ALU”

In this project, we design a 16 bit reversible ALU that can perform eight operations simultaneously. The eight operations include addition, subtraction, multiplication, division, AND, OR, NOT and XOR. All the modules are simulated in Questasim SE 6.5 and synthesised using Xilinx ISE 14.3.

2.“FIFO ( Using Verilog )”

There is one memory in which the sender store the data at his own clock rate.

This memory is read by the user /reciever on request and is available to it on the rate desirable by the reciever.

Simulation on QuestaSim and Synthesis on Xilinx ISE and implementation on Spartan 3E FPGA (Xilinx).

Indus tail Training :-

“ Embedded system”

To train engineering under -graduates on 8051 microcontroller, using C language programming and interfacing various peripherals in CETPA INFOTECH PVT LTD.

Attended Industrial training on NTPC KAHALGOUN, Bhagalpur for 15 days and enriched with the ability to learn Transmission & Generation in Power Plant.

To train 6 months Industrial training on 3ST Technology Pvt. Ltd, Noida.

Amrita Kumari



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