Verilog, SystemVerilog OVM and UVM

C.RANADHEER REDDY

D***, *rd Cross, **th Building

Manjunatha Layout, Marathahalli Phone No: +91-776*******

Bangalore-560037 Email id:****************@*****.***

Career Objective:

Seeking a challenging growth oriented position in VLSI domain (Design & Verification) where my technical skills and knowledge can be effectively utilized, eventually leading to the growth of the organization.

Experience:

Training experience on VLSI Design and Verification in Deep Thought Technologies in Hyderabad from Jan-2015 to Aug-2015.

Roles:

1)Understanding the concepts of different modeling techniques in Verilog.

2)Understanding the SystemVerilog concepts like Object oriented programming, constrained randomization, Assertions based verification, Functional coverage.

3) Understanding the concepts of Verification Methodologies like OVM and UVM.

Technical Skills:

HDL

Verilog

HDVL

SystemVerilog

Methodologies

OVM and UVM

EDA Tools

Xilinx ISE Design suite, Questa Sim

Scripting languages

Python, Perl

Programming Languages

C, C++

Academic Profile:

Course

Discipline

University/Board

Year

Percentage

M.Tech

VLSI-System Design

JNTUH

2014

86.50

B.Tech

E.C.E

JNTUA

2011

74.02

Intermediate

M.P.C

Board of Intermediate Education, AP

2007

85.80

10th

S.S.C

Board of Secondary Education, AP

2005

87.00

Projects

1)Verification of FIFO in System Verilog (UVM)

Description : FIFO is designed with 8-bit width and 16-bit depth by using read enable and write enable as control signals. The output of FIFO may be full, partial or empty based on control signals.

Roles:

Design using Verilog HDL.

Development of stimulus generator which transfers the data in terms of packets.

Development of input and output Interfaces with respect to DUT.

Development of active agent at input interface and passive agent to monitor the output.

Development of virtual sequence to control the sequences and sequencers.

Development of verification components like sequencer, driver, monitor, scoreboard.

Simulating and Debugging the test cases using Questasim Simulator

Languages and Tools used: System Verilog, UVM and Questasim

2)Verification of GMII Interface

Description : GMII stands for Gigabit Media Independent Interface. It provides an 8-bit wide data path between a 1000 Mbps PHY and a MAC sub layer. It consists of a stimulus generator that generates packets, Driver and Monitors which acts as transactors for the DUT and a Checker which compare the actual and expected transactions.

Roles:

Understanding the specifications and features of interface.

Development of verification environment.

Development of GMII Interface which acts like a Dummy DUT.

Development of Driver, Monitor, and Checker components.

Simulating and debugging the test case in Questasim simulator.

Languages and Tools used: System Verilog and Questasim.

3)Design and Verification of AXI4 Lite Interface in Verilog

Description : AXI (Advanced Extensible Interface) is the third generation of AMBA interface. It is targeted at high performance, high clock frequency system designs. In this interface I kept a small memory inside Master and Slave and verified the read and write transactions that are working properly through AXI interface.

Roles:

Understanding the features of AXI4 Lite

Preparation of the test plan and coding of test cases in Verilog HDL

Simulation and Debugging of test cases using Xilinx ISE Design suite.

Languages and Tools used: Verilog and Xilinx ISE Design suite.

Academic Project -M.Tech

FPGA Implementation of Selective Video Compression Based On ROI Using Gaze Location Prediction.

Description : The aim of the project is to selectively compress the football videos based on concept of Region of Interest (ROI) with the help of gaze location prediction principal. This is achieved through saliency extraction and shot classification of the video.

Publication : FPGA implementation of selective video compression based on ROI using gaze location prediction, in the journal of IJESR/October 2014/ Vol-4/Issue-10/766-771.

Academic Project -B.Tech

FPGA Implementation of Image Segmentation Processor

Description : The aim of this project is to segment the medical images and to obtain the required tumor part from it for the analysis of the tumor part. This is done with the help of k means algorithm.

Certification programs

Attended one day work shop on Vguru software in JBIT

Attended one week training program on digital control systems in broadcasting transmitters conducted by All India Radio.

Profile summary

Dynamic, Enthusiastic and performance driven person with excellent blend of leadership, communication and continuous learning skills.

Equipped with the ability to work among different group of people.

Comprehensive problem solving abilities.

Personal Details

Fathers name : Dr C. Chinnapu Reddy

Date of birth : 10-Dec-1989

Marital status : Single

Languages Known: English, Telugu and Hindi.

Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.

Place: Bangalore

Date:

(C Ranadheer Reddy)

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