Engineer Design

LAKSHMI DORAVARI

Email: acssnf@r.postjobfree.com Mobile: +91-966*******

Work Experience of more than 6 years in FPGA System Design including using soft/hard processors Microblaze and PowerPC. Exposure to complete FPGA Design cycle – Selecting device, Floor planning, RTL modules design and integration, functional simulation and board testing

EDUCATION

Years

Institution

Examination/Course

CGPA/%age

2014 - Present

BITS Pilani (Currently in 4th Semester)

MS, Microelectronics under WILP

6.6/10.0

2006 – 2007

Cranes Varsity

Advanced Diploma Course, Digital Signal Processing

B

2000 - 2004

Arunaii Engineering College(Affiliated to University of Madras)

BE, Electrical &Electronics

74.1%

2000

Sri Vidyaranya Junior College

Board of Secondary Education, Andhra Pradesh

74.3%

1998

Bharatiya Vidya Bhavan

Central Board of Secondary Education

74%

SKILLSETS

Domain Expertise:

FPGA Design: RTL design,Timing Closure,Functional simulation, board testing

RTL Languages:

Verilog, VHDL

Programming Languages:

C

EDA Tools:

Xilinx: ISE, EDK,Sysgen

Synopsys: Synplify Pro

Simulation tools: ModelSim, Active HDL, ISIM

I2C, PCIe, SPI, DDR3, AXI

Protocol Expertise:

Embedded Processor :

Microblaze, Power PC

Soft Skills:

Good communication, Team player, Quick Learner, Mentoring Skills, Interfacing with customers

WORK EXPERIENCE

Timeline

Organization

Designation

Domain

Jan 2014 - Present

Lattice Semiconductors Pvt Ltd

Applications and Design Solutions Engineer

FPGA Design and DSP algorithms implementation

Dec 2009 - Jan 2014

Alpha Design Technologies Pvt Ltd

Senior Systems Engineer

FPGA Design and DSP algorithms implementation

Dec 2007 - Dec 2009

Applied DSP

Design Engineer

Digital Signal Processing

Lattice Semiconductor Pvt Ltd (Bangalore, India)

Jan 2014 - Present

Applications and Design Solutions Engineer

Responsible for designing the following consumer solutions integrated with wearable devices. The designs targeted existing Lattice FPGA devices.

Pedometer Design

Fingerprint Detection

Voice Activity Detection

Got ramped up quickly in a newly formed team, took initiative and owned the complete design flows.

Responsible for creating the design level specs and owned algorithm development

Solely responsible for Verilog coding, integration of modules and board testing- Designs were successfully delivered to customers

Solely responsible for migrating the PCIe demo design from Lattice ECP3 fpga device to the newer ECP5 design.

The design consisted of integrating 5 digital IPs which were still in development stages with software tools which were beta versions

Took care of integrating the design and making it workable on the tool – was the first to use both the software and the IPs for the ECP5 device

Filed a good number of Software and IP bugs during RTL design, integration and testing – The design was successfully working

Supported various teams in bringing-up the subsystem on different platforms like hardware and software

Helped IP designer in improving the model and fixing the issues through continual feedbacks

Filed Diamond tool issues and enhancements for easier integration and debugs

ALPHA DESIGN TECHNOLOGIES (Bangalore, India) Dec 2009 - Dec 2013

Sr, Systems Engineer

Worked on Radar Systems projects like:

Monopulse IFF Receiver Design

Responsible for signal processing unit and Design Document preparation.

Designed and Implemented RTL Design on Board using Verilog and targeting Virtex 6

Spearheaded test jig creation involving using Microblaze and C language for testing the working of the DSPU before integration with RF -cut down debugging time by half

Owned Integration of the DSPU unit with RF system

Interfaced between the RF Group and the Digital Board Design Group

Radar Seeker Receiver Design

Spearheaded creation of FPGA design for one of the sub-systems.

Consolidated and Implemented using soft core Micro blaze, RTL coding using VHDL and using HDL coder for Filter design.

Writing test bench to verify design functionality and timing

Validating the design on the hardware on chip scope and oscilloscope

Owned Integration of the Radar Seeker unit with the System Control Unit

Interfaced between the RF Group,Digital Board Design Group and the System Control Unit

CDMA Encoder

Owned design of encoder data flow path.

Included development of RTL code in VHDL for CRC, HDLC and FEC Encoding.

Responsible for functional verification in simulation and on board

Development of power pc based test jig to implement the decoder blocks to verify functionality.

APPLIED DSP (Bangalore, India) Nov 2007 - Dec 2009

Design Engineer

MPEG2 Audio and Video Player

Responsible for integrating MPEG2 audio and video player using C coding and VC++ .

Hardware, software integration testing- Successfully Delivered

MP3 Audio Player

Responsible for porting MP3 code developed and implemented on VC++ to the BF537 platform using C and ASM.

Hardware, software integration testing- Successfully Delivered

Vocoder

Responsible for code development and implementation of CELP decoder for ANUDSP and ADSP2181.

Hardware, software integration testing- Successfully Delivered

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