Engineer Design

JIUNN-KAI WANG Phone: 623-***-****

***** *. **** **. 623-***-**** (Cell)

Glendale, AZ. 85304 E-mail: ************@*****.***

OBJECTIVE: Seeking a challenging Hardware Design Engineer position.

TECHNICAL SKILLS include:

Operating Systems: UNIX, Linux, Windows and DOS.

Microprocessors: Intel 8085, X86 (Pentium), AMD 29050, Freescale 68360, MPC 860, MPC8270, MPC5554, MPC8547E, MPC8548E, ARM926, PIC microcontroller.

DSPs: TMS320C5509, TMS320F2812, TMS320DM6467 (DMSoC), ADSP2191M.

Ethernet Switch: Vitesse VSC7462, VSC8504 PHY, Broadcom BCM 56014 (Ethernet Switch), BCM5248 (10/100Base-T PHY), BCM5482(GbE PHY),BCM5461(GbE PHY), etc.

Design Languages: C, C++, VC++, Code Composer, Assembly language, VHDL, Verilog,

Vender Tools:

Xilinx ISE 13.4, Actel Libero, Altera Quartus II, Quick Logic IDEs.

Synplicity Pro, Modelsim, NCSIM, ISIM.

Mentor Graphics: Design Architect, QuickSim, Boardstation, Hyperlynx, DxDesigner.

Cadence design tools: OrCAD, PSpice, Allegro.

MS Office/Visio, Visual C++ 2010.

MKS Source Integrity, DOORS, CVS, Clearcase.

Protocols: SONET, ATM, TCP/IP, 10/100/1000 Base-T Ethernet, ADSL, VOIP, VME, VXI, VPX, PCIe, cPCI, XAUI, FC, I2C, SPI, USB, CAN, GPIB IEEE-488/802.3, RS-422/232, ARINC 429, 1553(DDC Mini ACE), WiMAX (802.16).

FCC (EMI), NEBS, UL certification.

FAA DO-254, DO-178B, DO-160 certification.

PROFESSIONAL EXPERIENCE

UTC Aerospace Systems(Goodrich ISR), Albuquerque, NM. March 2014 till May 2015

Hardware design consultant (Contract)

Support C130J project’s BIU design upgrade to meet DO-254 requirements. MPC8548E based cPCI single board flight computer used on C130 aircraft. Board consists of DDR2 SDRAM, NOR Flash, 100Base-T Ethernet, DUARTs, DDC Mini-ACE Mark III for 1553 Interfaces.

FPGA design for MPC8548E local bus interface to DDC Mini-ACE Mark III for 1553 Interfaces.

Support engineering prototype bring up testing and re-design activities for flight SBC.

Stress analysis for the SBC.

Aviage Systems (work from home contract assignment) Feb. 2014 to Aug. 2014

Hardware Engineer (consultant)

Support C919 PCM (Power Conditioning Module) Actel FPGA functional simulation, code verification for DO-254 certification; Atmel CPLD functional simulation, code and binary file verification.

Attended weekly meeting with vender for PCM requirement review to meet DO-160G certification. Review CCR HW, GPM specification requirement, backplane design layout, etc.

UTC Aerospace Systems(Goodrich ISR), Albuquerque, NM. April 2013 till Dec. 2013

Hardware design consultant (Contract)

Support C130J project’s BIU design upgrade to meet DO-254 requirements. MPC8548E based cPCI single board flight computer used on C130 aircraft. Board consists of DDR2 SDRAM, NOR Flash, 100Base-T Ethernet, DUARTs, DDC Mini-ACE Mark III for 1553 Interfaces.

Support CODAS project’s data acquisition system(satellite rocket launch monitor) design activities. Design includes Vitesse VSC7462 (Ethernet Switch), VSC8504 (PHY), DDR2 SDRAM, SPI NOR Flash, Quicklogic’s anti-fuse FPGAs for 1553 control circuits and sensors inputs.

Schematic capture in Mentor Graphics’ DxDesigner, PADS PCB layout.

Cisco Systems, Milpitas, CA. March 2012 till March 2013

Hardware Engineer(contract)

Support Wanaka project - Connected Video Surveillance design activities. PCIe full height PC Board hardware design, unit testing. Four Digital Media SoCs (TMS320DM6467 – dual TMS320C64x+ DSP core, ARM926EJ-S Core) and TVP5154 video decoder capable of ITU-T H.264, MPEG-4, MJPEG compression video encoding up to 16 NTSC/PAL/SECAM video inputs.

SPARTAN 3 FPGA/DDR2 interface (Xilinx MIG20 DDR2 IP core, Verilog and VHDL combo) verification with ISIM, improve pblocks place & route with PlanAhead to eliminate VANC (checksum) error and video frame loss. FPGA design tool: Xilinx ISE13.4, ISIM, Plan Ahead.

Various security cameras design review and testing.

Gatemaster building security controller hardware testing.

Honeywell Inc. Phoenix, Az. June 2011 till Feb. 2012

Hardware Engineer (Contract)

Responsible for Gulfstream 450/550 aircraft MRC (Modular Radio Cabinet) NIM3 (MPC8270 based embedded Network Interface Module 3rd generation), APC (ADSP2191M based Audio Processor Card) hardware design, documentation, validation, HALT(Highly Accelerated Life Test), EMI and FAA certification activities.

Radio FPGA verification for NIM3 main processor board..

Xilinx/Altera CPLDs timing verification for weather radar RFM Transmitter and Receiver.

Rogerson Kratos, Pasadena, CA. Feb. 2011 till June 2011

Sr. Software Engineer

Developing embedded graphics software for aircraft cockpit display units. The SW runs on an Intel Celeron CPU with an 810 chipset used for the graphic displays. Performed SW Test Procedures (STPs), Code Review Dry Run, and completed SW Problem Reports (SPRs).

In charge of “Fuel Quantity” graphical display on EICAS and Composite display pages.

Each Display Unit has a screen size of 8” x 10” with a color LCD display resolution of 1024 x 768.

Tools: ANSI C, OpenGL, MS Visual C++ 2010, American Arium ICE, ARINC 429 Bus Analyzer & Simulation Tool by TechSAT, MKS Source Integrity, DO-178B level A, and CAD-UL Embedded Workbench, analog Input/Output (I/O) processing unit (Motorola 68332 microcontroller I/O board), & digital I/O processing unit (Motorola 68332 microcontroller I/O board).

Tellabs Operations, Inc. Naperville, IL. Nov. 2010 till Feb. 2011

Electrical Engineer (Contract)

Support SPM-C PCB design project for CSS (Central Switching System) Shelf.

SPMC board consists of MPC8547E, Flash ROM, DDR2 SDRAM, Broadcom’s BCM 56014 (Ethernet Switch), BCM5248 (10/100Base-T PHY), BCM5482(GbE PHY), BCM5461(GbE PHY), SFP 1000BASE-SX optical module etc.

Schematic capture with Mentor Graphics Board Architect, PCB layout with Mentor Graphics Boardstation (20 layers board design).

Design specification and test plan for board testing and bring up.

Meggitt Airdynamics, Corona, CA. Dec. 2009 till June 2010

FPGA Design Engineer (contract)

Support hardware development design activities for Pneumatic System Controller AEH as used on the Embraer Legacy 450/500 Aircraft.

Timing analysis for the PowerPC MPC5554 and peripherals (ADC, DAC, SSRAM, FPGA, ARINC 429, WDT, etc.) with SynaptiCAD Timing analysis tools.

VHDL code design for RTL synthesis on Actel ProASIC3 with Libero IDE (Synplify Pro), Testbench design and simulation with ModelSim.

Hardware Requirement Document and Hardware Design Document including Analyses and Traceability for IO Board FPGA to support SOI audit, lab testing and DO-254 certification.

Verify the control hardware electronic to meet DO-254 level-A airborne electronic hardware design assurance guidance. Support software/firmware testing to meet DO-178B software considerations in airborne systems and equipment certification.

DOORS requirement management tool.

Aerojet, Sacramento, CA. Dec. 2008 till July 2009

Sr. Electrical Hardware Engineer (contract)

Support SM-3 anti-missile (kinetic energy interceptor) actuator simulator hardware development.

Duty includes VHDL/Verilog code design for RTL synthesis for Spartan-3 FPGA (Opal Kelly XEM3010, XEM3050), simulation and close-loop signal processing with actuator simulator.

Xilinx ISE, ModelSim, Opal Kelly FrontPanel XML code design.

Actuator(PWM drive) simulator CCA hardware analog circuit design using current sensors and OP AMPs for inertia, torque, velocity and gain control for actuator position, speed, direction. A/F converters to provide digital signal processing resource; D/A converter to provide close-loop feedback to keep track of the actuator pintal position. Lab testing equipments (power supply, oscilloscope, logic analyzer, etc.);

Active Secret Clearance.

Hughes Network Systems, Gaithersburg, MD March 2008 till June 2008

FPGA Design Engineer (contract)

Support Mobil SAT project DSS(Distribution Super Frame) FPGA development.

VHDL code design for RTL synthesis, integration of PCI core with custom logic into Xilinx Virtex 5 LX110 FPGA on VMETRO FP05 (PMC card fitted in HP G5 network server).

Xilinx ISE 9.2.04i, Modelsim, Cadence NCVHDL, Simvision. Red Hat Linux 5 platform.

Clearcase file version management system.

Parker Hannifin, Irvine, CA Nov. 2007 till Feb, 2008

Hardware Design Engineer (contract)

Support P20 (corporate jet) hardware design project: Electro-hydraulic flight control equipment hardware design.

TMS320F2812 DSP based digital circuit design, Actel ProASIC FPGA design, low-voltage analog circuit design for electro-hydraulic solenoid actuator control circuit design using OP AMPs, ARINC 429, RS-485 communication data link design.

Hardware design to meet DO-254 airborne electronic hardware design assurance guidance certification and DO-160 lighting protection requirement.

Design tool: DxDesigner, Allegro layout software. DOORS requirement management tool.

Wireless Highways, Inc. Falls Church, VA. May 2006 till Aug. 2007

Principal Electrical Engineer

Wireless broadband (Beam Former, WCDMA, WiMAX 802.16) application hardware design in ATCA platform. Digital interface design with radio (2.2G, 2.4G). Power management implementation on CPLD.

MPC 8270, SDRAM, DPRAM, Flash memory, PCI/PCIe bridge(PEX8111), PCIe switch( PEX8532), Virtex 2, Virtex 4, Spartan 3 FPGAs, CoolRunner CPLDs, Optical modem, optical interface for radio(1.25G/2.5G, WCDMA, WiMAX, 802.16), SERDES (to radio), Fast Ethernet, USB, etc.

Design tool use Xilinx ISE, Altera Quartus II for VHDL code design for RTL synthesis, test bench design and simulation for processor, DPRAM, DSP core(generated by MATLAB, Simulink) for Beamformer uplink/downlink functionalities.

OrCAD/pSPICE for schematic capture, Allegro for board layout. Lab tools digital oscilloscope, logic analyzer and spectrum analyzer.

Rockwell Collins, Cedar Rapids, IA. Aug. 2005 till March 2006

Electrical Engineer (contract)

VPX based Future Combat System Large Network Processor WCA design for Current Combat Force. Integration of SPRM (with GbE), GESM(GbE switch).

VPX based Future Combat System Common Network Processor WCA design for Future Combat Force. Integration of SPRM (with GbE, PCIe), GESM (XAUI, GbE), ASFM (PCIe, ASI),

EOM (electrical to optics, XAUI, XFI, GbE, ASI) board design.

Use Mentor Graphics’ DxDesigner, PADs layout tool, Hyperlynx signal integrity analysis.

Northrop Grumman Corporation, Baltimore, MD. Sep. 2004 – May 2005

Hardware Engineer (contract)

Support F-16 project.

FPGA/CPLD design in VHDL, synthesis and test bench design for simulation with Modelsim.

Parameter Encoder interface to RF-IF Converter, PSpice simulation for filter circuits, High speed Flash A/DC, D/AC, PLL, ECL, RS485, MIL-STD-1553 interface for Navy aircraft(F-18),

CCA design, VME based SRA verification and WRA integration test with NI LabView.

EMI test to meet MIL-STD-810 standard.

Use Mentor Graphics Design Architect for schematic capture, Boardstation layout tools, Hyperlynx for signal integrity analysis.

Xilinx ISE, Synplicity, ModelSim for FPGA design, simulation.

Clearcase file version management system.

Custom Manufacturing and Engineering, Inc. St. Petersburg, FL. March 2003 – Sep. 2004

Hardware Design Engineer

TMS320C5509 DSP based high speed digital circuit board design, USB, I2C, DDR RAM.

FPGA/ CPLD VHDL code design for RTL synthesis, test bench design, simulation with ModelSim, Xilinx ISE tool, CVS file management system.

PC/104+ based Multifunctional Intellegent Remote Sensor System (MIRSS) hardware development. Ruggedized design package used in military C4ISR application.

Integration with IRIDIUM Satellite pager and image transmission.

Telemetry equipment design for Army peoject.

Video interface design (Standard Definition, MPEG-2).

Battery operated image sensor system with MOSFET power switch control.

OrCAD for schematic capture,

AG COMMUNICATION SYSTEMS, Phoenix, AZ. April 1994 - Nov. 2001

Staff Engineer

VHDL code design for RTL synthesis (Synplicity), test bench design for simulation with Modelsim for Xilinx, Altera, Quick Logic’s FPGAs, CPLDs.

GTD-5 fault tolerant network expansion projects, 68360 based embedded videoconference equipment (MPEG-2 over SONET/ATM, FCC class A), 68360 based embedded magnetic tape drive interface (cPCI ), and PowerPC 860 based embedded system iMerge (VOIP, NEBS compliant, cPCI based) projects.

Designed clock/power distribution card for in-building TDMA wireless system. Intensive testing to meet FCC class A regulatory requirement.

Designed high-speed backplane, POTS splitter filter for ADSL projects (FCC class A).

SONET/ATM Crossconnect System: use 68360 embedded processor, ASICs and ECL/PECL high-speed logic circuits to design OC-3 (155.52 Mbps) optical line card and components placement.

HONEYWELL, INC., Phoenix, AZ. Sep. 1990 - April 1994

Flight control, avionics equipment manufacturer.

Sr. Project Engineer

Design high speed data loader with TAXI Interface for 777 AIMS cabinet.

29050 based embedded SAFEbus Resource: design SAFEbus interface, high speed TAXI interface (125 Mbps), MACH(CPLD, AHDL design) for use as data loader and communicate with other modules in the 777 AIMS cabinet via SAFEbus.

VXI TAXI interface module: use AMD TAXI high-speed chip set (125 Mbps), MACH(CPLD, AHDL) design in a VXI C-size form factor.

C, assembly language programming to bring up the data loader.

AG COMMUNICATION SYSTEMS, Phoenix, AZ. Oct. 1988 - Sep. 1990

Member of Technical Staff

386 Processor Complex: fault tolerance central office switching system digital circuit design.

Packaging Technology Enhancement: digital circuit design. Use ASICs and PLDs to reduce unit size, cost and power consumption.

ASIC verification with Mentor Graphics Quicksim.

FUJITSU BUSINESS COMMUNICATIONS, Anaheim, CA. Aug. 1983 - Nov. 1987

Sr. Design Engineer

Circuit boards functional test fixture design and test program development.

Design several test fixtures, test programs for PBX circuit packs.

Develop PC based ATE Systems, use IEEE488 controlled test equipments.

WANDEL AND GOLTERMENN INSTRUMENTS, Livingston, NJ May 1981 - Jan. 1983

System Hardware Engineer

Analog circuit design for Tone Generator (OP AMPs, Oscillators, PLL, etc.),

digital circuit design, CODEC/filter test interface design, circuit board design.

ATE system development.

EDUCATION:

MSEE, New Jersey Institute of Technology

BSEE, Taiwan National Oceanic University

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