Design Project
Resume:
RESUME
KUNTIGORLA NARESH
Mobile No: +91-990*******
Email ID: ***********.***@*****.***
CAREER OBJECTIVE
Every assignment taken up by me, I consider it as a unique opportunity to create and add value through a hands-on learning approach. I wish each one of such, to contribute to the growth and objectives of my Organization, by way of achieving my own career growth.
TECHNICAL SKILLS
Electronic Design Packages : Xilinx ISE Design Suite 14.2.
Programming Languages : Verilog, System Verilog, VHDL, and Basic C.
Verification Methodology : SV and UVM.
Microcontrollers / FPGA : FPGA [Spartan 3E, Spartan 6].
Software Tools : ModelSim 6.4a, Questasim 10.2c.
Familiar Protocols : UART,SPI.
Familiar OS : Windows, Linux.
PROFESSIONAL COURSE
I Completed Certified training program in VLSI Design & Verification from Sandeepani School of VLSI Design.
Digital Design
Verilog
FPGA
Functional verification
System Verilog
EDUCATIONAL DETAILS
Degree/ Course
Institution
University / Board
Year of Passing
%Marks
M.TECH(VLSI)
Avanthi’s Scientific Technological& Research Academy,gunthapally, Hyderabad
JNTU,Hyderabad
2014
81%
B.TECH(E.C.E)
Nishitha college of engineering and technology, lemoor, Hyderabad
JNTU,Hyderabad
2012
73.48
Intermediate(12th)
Suguna junior college, Kodad, Nalgonda
Board of Intermediate education(A.P)
2008
89.2
S.S.C(10th)
Zilla Parishath high school(ZPHS), Ganapavaram(K), Kodad, Nalgonda
State board for secondary education(A.P)
2006
80.8
PROJECTS
1. Title of the Project: Booth multiplier and Universal shift register IP design and implementation in FPGA
Description: The aim of the design a multiplier, which can multiply two n bit signed number in 2’s compliment form. The Universal shift register IP design, which can performs the eight shift operations.
Software Tools: ModelSim, Xilinx ISE.
Hardware: Spartan 3E.
2. Title of the Project: Design and verification of FIFO
Description: The aim of this project is to design a FIFO and create verification environment for obtaining total coverage.
Software Tools: Questasim, Xilinx ISE.
Hardware: Spartan 3E.
3. Title of the Project: FPGA based implementation of image edge detection using CANNY edge detection algorithm
Description: A Methodology for implementing real-time DSP applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) for Matlab is presented in this project. It presents architecture for Edge Detection using Sobel Filter for image processing using Xilinx System Generator. The Edge Detection method has been verified successfully with no visually perceptual errors in the resulted images.
Software Tools: Xilinx ISE 10.1i, Xilinx system Generator, MATLAB.
PERSONAL PROFILE
Father Name : K Lingaiah.
Date of birth : 6th February 1991.
Gender : Male
Current Address : H.No.13/11,balavidya nilaya,10th cross,
Tulasi theatre road,Marathahalli,Bangalore.
Contact No : 095********.
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Place : Bangalore Signature of the Candidate
Date :
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