Design Engineering

B.RAJENDRA PRASAD

H.NO: **-***, P & T Colony, Mobile: +91-879*******

Dilsuknagar, Hyderabad-500308. Email: *****************@*****.***.

Objective

To work in an environment that would enable me to utilize my knowledge, commitment, hard work and also provide an ambience to sharpen my skill set in VLSI Domain.

Synopsis

Master of Engineering from Chaitanya Bharathi Institute of Technology, Hyderabad.

Ability in learning new concepts quickly, working well under pressure and communicating ideas effectively.

Team player with ability to work independently & have strong analytical, leadership, interpersonal skills as well as ability to work effectively in fast placed environment.

Training

Institute : LUCID VLSI ACADAMY.

Course : Advanced Digital Design.

Tools : Modelsim, Questasim.

Topics Covered : Multiplexer, Counter, Comparators, State Machines etc.

Technical Knowledge Acquired

Strong foundation in Digital Design Concepts.

Sound knowledge of Digital Circuits.

Knowledge of C, Verilog.

Academic Profile

Master of Engineering with “8.58 (CGPA)” from Chaitanya Bharathi Institute of Technology, Hyderabad.

Bachelor of Technology with “74.5%” from Princeton college of Engg & tech, Ghatkesar, Hyderabad

Intermediate with “84.5%” from Narendra Jr College, Metpally.

SSC with “80.5%” from Z.P.H.S, Thalla Rampur.

Achievements

Part of the Organizing committee of “VLSI Design Using cadence” Workshop which was conducted in our college.

Got center topper certificate from Z.P.H.S for 10th.

Secured Score of 404 in GATE’ 12.

Professional Experience: 1 year

Intern Technical at DRDO (Defense Research and Development Organization), Hyderabad.

Project1:

Project Title : Design and Simulation of 12 bit Current Steering DAC.

Description :

The current steering DAC architectures help in keeping the load current (i.e. current drawn by the DAC) constant, and in achieving a higher speed of operation. Keeping these considerations in view, a 12-bit segmented current steering DAC has been designed. The DAC has been divided into four segments of 3-bits each. One segment caters to lower LSB 3-bits of input digital word, second segment caters to LSB 3-bits of input digital word, third segment caters to upper LSB 3-bits of input digital word and the last segment caters to MSB 3-bits. The design will be implemented in a state of the art 180 nm process, with a supply voltage of 3 V and at a sampling speed of 2 GHz.

Tools Used : Cadence Virtuoso Schematic Editor.

Technology : 65nm, 180nm.

Project2:

Project Title : Design and Implementation of Digital clock using Verilog HDL.

Description : Designed the Digital Clock using multiple counters and

Implemented complete functionality of digital clock in Verilog and

Checked for all corner case scenarios.

Role : Digital Design.

Tools Used : Modelsim, Questasim.

Personal Details

Father’s Name : Mr. Swamy

Mother’s Name : Mrs. Rajamani

Date of Birth : 21-06-1990

Nationality : Indian

Sex : Male

Hobbies : Reading Books, Playing and Watching Cricket.

Declaration

I hereby declare that the above mentioned information is true to the best of my knowledge.

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Date:

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