Engineer Design

Rahul Sharma Email ID:- **************@*****.***

Address - H.No. 316, Sector 10A, Gurgaon Contact No:-+918*********

(Haryana- 122001)

“RTL Designer, with keen interest in VLSI. Looking for challenging position with a growth oriented organization where I can enrich my experience and broaden my horizon and use my knowledge and skills to impact company’s growth.”

EXPERIENCE SUMMARY:

Overall experience of 2 years in Digital/RTL Designing.

Designed and Verified SRAM Controller Ingress FPGA [MachXO2 4000] for OMAP4460 Processor.

Designed and Verified Flash Controller for OMAP4460 Processor.

Verified RGB and RFBI Blending data through UVM Environment.

Designed and Verified I2C Slave block towards MAX-II CPLD.

Designed Controller for handling Power, Clock and Reset Management towards Network Interface Card for LS2 Processor.

SKILL SET:

Languages: VHDL / Verilog HDL, PERL, Tcl, C, UVM.

Simulators : Xilinx ISE Simulator, Active HDL Simulator, ModelSim VHDL/Verilog, System Verilog Simulators

Platforms: Xilinx Planahead v14.4, ModelSim v10.2, Lattice Diamond v3.1, Altera Quartus II v15.0.

Memory: SRAM, NAND Flash

Protocols: I2C, SPI, GPMC (General Purpose Memory Controller) Bus, RFBI.

EDUCATION:

Post Graduate Diploma in Embedded System Design (PG-DESD) from CDAC in 2014 with 68.57%.

B.Tech in Electronics & Communication in 2013 with 71.86%.

12th in year 2009 with 74.33%.

10th in 2007 with 70%.

Professional Experience

VLSI Engineer at VVDN Technologies Pvt. Ltd. (2 year)

SLVU_SC38 (Silvus Technologies)

Scope: The SC3822 Digital Board is designed to be used in Silvus Technologies MIMO Radios. The SC3822 digital board is to be designed around Xilinx Zynq-7000 series All Programmable SoCs. The board shall have on board boot flash, DDR3L RAM, temperature sensor, EEPROM, JTAG.

Created the VHDL Testbench for verify RTL design.

Hardware bring up and Modified the RTL Code for debug on board issues.

Synthesized the modified RTL code on Xilinx ISE and implement the netlist on Xilinx Implementation tools targeting to Xilinx Zynq-7000 series.

BSQI_USNA (Bisquare Systems Pvt. Ltd.)

Scope: The scope of the FPGA Block is to provide the necessary “Glue logic” to interface the OMAP Processor and several interface like NAND flash, SRAM etc. FPGA had a 16 bit interface to OMAP, and a 8 bit MLC NAND memory connected to the FPGA. The Memory mapped to GPMC local bus address range so that OMAP can access the RAM through FPGA as its local bus memory.

Designed and verified the SRAM and Flash interface for the OMAP4460 Processor.

Synthesized the RTL code on Lattice Diamond and implement the netlist on lattice Implementation tools targeting to MachXO2 4000 series.

Integrated all functional RTL modules and created a system level top. Tcl scripts where written to manage the files and testbench.

SKHU_HCAM (Skully Helmets Inc.)

Scope: FPGA is used to drive the LCD without the intervention of processor. This facilitates instant video availability in the LCD upon power-on reset. FPGA works on the LCD controller Output .Also FPGA block provides necessary logic to create on screen display in helmet. The design includes proper reception of overlay RGB data from OMAP processor, blending it with original data stream and driving the helmet display. The design will also include an LPDDR controller for frame buffer memory.

Created the UVM Environment for verify the RTL Design.

Created a detailed test-plan to verify the (Blending Block) RTL and verified the RTL as per the test plan.

Tcl scripts where written to manage the files and test cases.

FSLU_NVMe (Freescale Semiconductor India Pvt. Ltd.) – NIC Card

Scope: LS2085A based Intelligent SSD Card is a NVMe compatible Intelligent SSD Card in a PCI Express form factor meeting or exceeding specifications defined by Freescale. This is a 2 board solution where Ls2085A is in the main board which is described as NIC Card (Network Interface Card) where as FPGA and the NVDIMMs are sitting on Storage Card. The device will be enumerated as a PCIe Gen3 device. For Accessing the Registers of NIC Card and Storage Card I2C Interface is used.

Modified and verified the I2C slave for the LS2 Processor.

Designed FSM for power sequence, clock selection, reset management and for communication between NIC and Storage Card CPLD through HSMC.

Synthesized the RTL code on Quartus and implement the netlist on Quartus Implementation tools targeting to MAX-II series.

Integrated all functional RTL modules and created a system level top. Tcl scripts where written to manage the files and testbench.

FSLU_NVMe (Freescale Semiconductor India Pvt. Ltd.) – Storage Card

Scope: The FPGA (Stratix V) logic enables the data movement from Host PC via LS2 to the NVDIMM connected to FPGA. The interface between LS2 and FPGA is via PCIe Gen2.0 Interface. The flash controller act as an interface module between PCIe and DIMM module which is having 4 flash IC’s.

Designed Data_IN and Data_OUT generator for NVDIMM having 4 flash IC’s. Both Generators provide support for Asynchronous and NVDDR2 interface.

Create the PCIe based testbench model for testing the nand simulation model.

Integrate with other modules like DMA, Descriptor Controller and Command Address Module.

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