Project Design

D.SINDHU

Email: ************@*****.***

Phone:+91-906*******

Objective:

To work on a challenging project which provides an opportunity to enhance my technical skills and knowledge, this could provide me an insight into new aspects so that it would be helpful for my career.

Training Undergone

Underwent PCB DESIGN& EMBEDDED SYSTEMS Training in MYTECTRA PVT.LTD in Bangalore.

Software Skills:

As the part of Training I have undergone the following.

1.PCB DESIGN

MODULES:

Orcad schematic.

Orcad layout.

Orcad capture.

Signal Intigrity and EMI

2. EMBEDDED C

Other Skills

Programming Languages known are C.

Operating Systems known are MS Windows 98/XP.

Micro Processors known are 8085, 8086 and Micro Controller 8051.

Basic knowledge in Verilog.

Academic Profile:

Course

Name of the Institution

Name of the Board/University

Percentage of Marks

Year of passing

M. Tech

(Embedded Systems and VLSI Design)

Sri Krishna Devaraya University, Ananthapuram.

Sri Krishna Devaraya University, Ananthapuram.

79.00

2015

B.Tech

(ECE)

J.B women’s engg. college,

Tirupati.

JNTU

Ananthapur.

70.40

2013

Inter (M.P.C)

Sri Chaitanya junior college,Tirupathi

Board of intermediate Education, AP.

85.30

2009

SSC

Z.P.H.School,k.v.palli.

Board Of Secondary Education,AP.

86.00

2007

M.TECH PROJECT_PROFILE

MAIN PROJECT

Project Title : PARRELLEL TURBO DECODING FOR HIGH THROUGHPUT WIRELESS SYSTEMS

Environment : VLSI

Team members : 1

Project Period : August-April 2015

Description : The sensor nodes of a wireless sensor network (WSN) are typically required to maintain sporadic but reliable data transmissions for extended periods of time. However, in applications the sensor nodes have to be small, preventing the use of bulky batteries. The outstanding forward error correction capabilities of turbo codes made the part of many today’s communications standards. And also turbocodes has recently been considered energy constrained wireless communication applications, since they facilitate low transmission energy consumption. In this paper, a new low complexity ACS (add compare and select) architecture is introduced in the proposed design. The proposed turbo decoder is based on the LUT-Log-BCJR architecture. Entire decoded architecture is coded using Verilog HDL and it is synthesized using Xilinx EDA with Spartan 3E FPGA.

Co-curricular activities:

Volunteer in all the activities of ACE Students forum of EC.Dept.

Organizing the annual college day. Conducted various events.

Represented college in various fests.

Strengths:

Dedicated and Hard worker

Logical thinker and Quick thinker

Time and Cost Conscious

Adaptability to changing environment

Self Starter and a Go Getter

Positive Attitude

Personal Profile:

Date of Birth : 06-03-1992

Nationality : Indian

Father’s Name : D.Venkatramana reddy

Mother’s Name : D. Syamala

Languages known : English, Telugu

Declaration:

I here by declare that the information furnished above is true to the best of my knowledge

Place: Bangalore

Date:

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