Physical Design Engineer

PRATEEK BANGALORE ESHANNA

*** ********* **., *****, ** – 75075 480–840–5117 *******.*******@***.***

Summary

Electrical Engineering Graduate actively seeking a full time opportunity in the field of Physical Design, Digital Circuit Design, and Design Automation.

Education

Arizona State University, Tempe, AZ Fall 2013 - Spring 2015 Master of Science (MSE) - Electrical Engineering in Mixed Signal Circuit Design.

Visvesvaraya Technological University, Belgaum, India Fall 2008 - Spring 2012 Bachelor of Engineering (BE) - Electronics and Communication Engineering (ECE). Technical Skills

Programming Languages: Verilog, System Verilog, PERL, TCL, Python, C, C++.

Tools: Cadence Encounter, Cadence ICFB, Cadence Virtuoso, Cadence Spectre, Cadence Calibre, Primetime, Hspice, Hercules VUE, StarRC, Aldec Active HDL, Cadence Encounter Characterizer, Cadence Abstract generator, Riviera PRO, ModelSim, GEM 5.

Design of a 16x32 Register File Array – VLSI Design Academic Projects

Designed a 16 entry 32 bit wide register file array with 2 read ports, 1 write port by verifying its operation for readability and writability using the SAED-PDK 32nm technology in Cadence Virtuoso tool. Also designed the read and write decoders to decode the address lines using the predecoding design.

Full ASIC Flow Design of a 32 bit multi cycle MIPS Processor (RTL to GDSII)– VLSI Design Designed and synthesized a 32 bit multi cycle MIPS Processor using RTL coding (Verilog) and followed the ASIC Design flow using the Auto Place and Route (APR) tool Encounter(PNR, CTS, Floorplanning) and analyzed the STA using Primetime tool.

Design, Characterization and Abstract generation of Standard cell library (32nm PDK) – VLSI Design Development of 32nm Standard cell library. Usage of Cadence library characterizer to find out the worst case vectors for delay/power. Usage of Abstract generator to generate an abstract view of the layout to be used by the PNR tool. Standard cells designed: INVx11, FADDx05, LATHFx01.

Implementation of an Asynchronous FIFO and its Verification – Advanced Hardware Systems Design Implemented a 32x8 Asynchronous FIFO (First In First Out) with write frequency of 100MHz and read frequency of 10MHz and verified it using a self checking layered testbench in System Verilog in Aldec Active-HDL tool.

Implementation of single cycle MIPS Processor – Advanced Hardware Systems Design Implemented a single cycle MIPS Processor and verified its operation for various instructions using Verilog in Aldec Active- HDL tool.

Development of Verification Testbench for a 4-Port Super Switch – Advanced Hardware Systems Design Implemented a self checking random driven testbench for the switch design of an asynchronous FIFO with 1 input port and 4 output ports. Test bench was made self checking through checker routines within the scoreboard. The tool used was Aldec Active-HDL.

Implementation of new cache replacement policy – Computer Architecture - 1 Implemented 2 bit Static Re-Reference Interval Prediction (SRRIP) block replacement policy instead of the traditionally used LRU policy. The performance of these 2 cache replacement policies were analyzed by running various benchmarks. The tool used was GEM 5.

Design of a Low Drop Out (LDO) voltage regulator circuit – Analog Integrated Circuits Designed a Low Drop Out voltage regulator which regulated the power supply voltage from 2.5V to 2.25V using the TSMC 300nm technology in Cadence ICFB tool.

Undergraduate Project

Natural User Interface (NUI) for TV using Kinect Designed and Implemented a very innovative technology using the device Kinect interfaced with TV where the user could control the TV using his voice commands and simple hand gestures. Presented a paper on this project in a National Conference at Manipal Institute of Technology, India and obtained the Best Paper award for the presentation.

Graduate Courses

VLSI Design, Digital Systems and circuits, Computer Architecture–1, Advanced Hardware Systems Design, Analog Integrated Circuits, Advanced Analog Integrated Circuits.

Work Experience

Worked as a Systems Engineer Trainee in Infosys Technology Ltd. from March-2013 to June-2013. In this period was trained on the basics of JAVA and RDBMS using the ECLIPSE IDE.

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