ASIC design, rtl,verilog coding

SUMANGALA.N

#**/* ***. **. ******’s church,

*nd cross road, Robertsonpet,

K.G.F-563122.

Mob: +91-897*******

E-mail Id: *****************@*****.***

Career Objective

To continuously enhance my knowledge, skills and experience by getting involved in challenging work environment and utilize them for personal and organizational growth to the best of my ability.

Educational Qualification

QUALIFICATION

UNIVERSITY/BOARD

SCHOOL/COLLEGE

YEAR

Stream/Degree,

Specialization

SCORE

Postgraduate

Visvesvaraya

Technological university,

Belgaum.

REVA Institute of Technology and Management,

Bengaluru.

2015

M.Tech.

(VLSI Design and Embedded System.)

77.87%

Undergraduate

Visvesvaraya

Technological university,

Belgaum.

Dr.Thimmaiah Institute Of Technology,

Kolar Gold Fields.

2013

B.E.

(Electronics & communication Engineering.)

74.6%

2nd Pre University

Pre University, Bengaluru.

KGF PU College,

Kolar Gold Fields.

2009

Physics, Chemistry,

Maths, Biology

75.8%

CLASS 10

KSEEB,

Bengaluru.

Sree Mahaveer Jain School,

Kolar Gold Fields.

2007

88.80%

Technical Qualification

Programming Languages : C, Hardware description language, TCL scripting language.

Tools Used : XILINX, MATLAB, Turbo-C, Linux-Cadence, Wish 84, Flash magic, Keil.

Operating Systems :Windows XP/7,Linux.

Other Packages :M.S.Word, Ms- Excel, PowerPoint, etc…

Extracurricular activities

Participated in Anti-smoking campaign conducted by ETHNUS in 2010.

Attended workshop on Ethical Hacking And Information Security conducted by

Security Guru.

Completed Networking course from ROOMAN Institute.

Attend workshop on Digital Design and Verification from 24th February 2014 to 01st March 2014.

Won 1st prize HDL programming competition conducted by Force of REVA for communication and electronics on 22 March 2014.

Academic project

During Master of Technology

Project.

Project title: Implementation of split array based charge scaling DAC.

Software used: Cadence virtuoso 6.1.5.

Description : DAC designed can be used as standalone device in WSN transceiver or used in SAR

ADC consuming less power and area.

Mini Project.

Project title : Design of I2C Master Bus Controller.

Software used: Xilinx 14.2 version.

Description : For Serial data communication, there are protocols like RS-232, RS-422, RS-485, SPI

for interfacing high speed and low speed peripherals. These protocols require more pin

Connection in the IC (Integrated Circuit) for serial data communication. To overcome this

Problem, the I2C protocol was used which requires only two lines for communication.

Mini Project.

Project title : Skew and power reduction using tunable clock buffers and inverters.

Software used: Cadence virtuoso tool.

Description : The two important design parameters considered in clock design is clock skew and power,

it has the highest switching activity and consumes major part of the total system power. As

the technology shrinks, clock skew consumes larger part of clock period and also leakage

power increases due to sub-threshold leakage current. The design of tunable clock buffers

and inverters that can be used in clock tree synthesis to reduce clock skew and power.

During Bachelor of Engineering.

Project carried out at Bharath Earth Movers Limited, KGF.

Project Title : Embedded Design For Power Optimization Using Power Saving System.

Components used: AT89C51 microcontroller, relays, 555 timer, PIR sensor, LDR.

Description :This project controls the speed of the fan with respect to room’s temperature &

intensity of Bulb is controlled by darkness of the room and prevents unnecessary

power wastage in the absence of human.

Technical Papers Presented

The paper titled “Survey on DAC used for Charge redistribution ADC”, based on this work has been published in the “International Journal of Research and Development Organization (IJRDO), ISSN: 3967-0867, Volume-2, Issue-3, March 2015”.

The paper titled “Implementation of split array based charge scaling DAC”, based on this work has been published in the “International Research Journal of Engineering and Technology (IRJET), E-ISSN: 2395-0056. Volume: 02 Issue: 05, August 2015.

Skills

Good coding skills in Verilog and analog design of mixed mode signal system.

Good knowledge in cadence front end and backend design.

Personal Details

Name : Sumangala.N.

Date of Birth : 04.03.1992.

Father’s name : Narayana Reddy.

Mother’s name : Shanthamma.K.Y.

Gender : Female.

Nationality : Indian.

Marital Status : Single.

Language Known : English, Hindi, Kannada, Telugu &Tamil.

I hereby solemnly declare that all the information duly furnished is absolutely true to the best of my knowledge, understanding and ability

Thanking you, Yours Faithfully,

(SUMANGALA.N)

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