Process Computer Science

Jose Montoya

916-***-**** – (C)

***********@*****.***

CAREER OBJECTIVE

To obtain a position as a Mask Designer at a Leading Semiconductor Company

QUALIFICATION

** ***** ** ********** ** physical design (CMOS), IC layout mask design and verification, digital experience and also basic experience in analog layout.

Solid layout experience in floor planning and power planning, place and route of large digital blocks, standard cell planning, hierarchical layout assembly, RV violation fixes.

Highly adaptable to ECO’s, strong communication skills in addition to working efficiently with other members of the team (DE, DA, and managers/supervisors).

Major tools:

1.Genesys, QEA (auto route tool), DFM, ANTARES (metal fill), CPDS (Intel LV tool), Macro/Mega Layout Verifications, DRC, LVS, ERC, DENSITY, IPALL (nac/antenna), netlist ECO tool to implement ECO changes, VUE tool to locate power shorts.

2.Cadence Virtuoso for Transferring Circuit Logics (Schematics) to Physical Designs

3.ICC; used ICC tool to implement ECO’s and clean all flows for layout structures.

Solid knowledge of UNIX platform and PC/WINDOWS platform.

Programming/scripting: UNIX, Perl.

PROFESSIONAL EXPERIENCE

MASK DESIGNER

INTEL CORP – FOLSOM, CA: 07/25/2005 - 07/15/2015

I worked for Intel Corporation from 65 nm process through 10 nm process. I supported the SRAM team by drawing customized standard cells (device level), and implementing Layouts for the blocks needed by the tool (compiler) to generate the SRAM top levels. I was also assigned to debug abutting issues until all the top levels were almost LVS clean and ready for the team to clean the remaining issues. Worked on DRC and LVS clean-up, ECO implementation, DFM issues, RV issues and cleaned all the flows at top level before sending the blocks to the FUB. As the team was moving to the next SRAM project, for several weeks I was assigned to work on DAC and DDR projects. For these projects I drew analog and digital cells and cleaned DRC, LVS and DENSIY issues on assigned layouts and other existing blocks.

-01/2014 – 07/2015 – Developed SRAM, layout for 10 nm process.

-11/2012 – 01/2014 – Developed SRAM, layout for 14 nm process.

-08/2010 – 11/2011 – Developed SRAM, layout for 22 nm process.

-06/2009 – 08/2010 – Developed SRAM, layout for 28 nm process.

-03/2008 – 05/2009 – Developed SRAM, DAC, DDR layout for 32 nm process.

-01/2007 – 03/2008 – Developed SRAM, DAC, DDR layout for 42 nm process.

-07/2005 – 01/2007 – Developed Encino DDR layout using 65nm process.

EDUCATION

CERTIFICATE IN AUTOMATED SYSTEMS (American River College).

AC/DC Theory and Circuit Fundamentals

Mathematics for AC/DC Circuits Fundamentals

Mathematics for Semiconductor Theory

Laboratory Practices and Techniques

Semiconductor Theory

Analog and Digital Integrated Circuit Application

Topics in Electronics New and Emerging Occupations

Advanced Student Projects and Laboratory

Basic Microprocessors

Introduction to Computer Science

Introduction to Personal Computers for Electronic Technician

Circuit Review and Applications

Programming for Electronics Technicians Using Visual BASIC

Digital Electronic Systems

Introduction to Electronic Communications

Fiber Optics and Communication Cabling

CMOS LAYOUT COURSES:

CMOS I

CMOS II

Topics in Electronics Technology (Mask Design Overview)

Topics in Electronics Technology (CMOS III – Autorouting)

Linux Operating system

Intermediate Linux Operating system

CADENCE EXPERIENCE: (old version)

Used cadence layout tool to draw layout cells in CMOS II class.

Used cadence layout tool for a couple months at Intel corp.

REFERENCES

Bee Ngo 512-***-****) *********@*****.***

Dean Cabrey (916- 895-1349) ****.*.******@*****.***

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