Design Project
Resume:
RESUME
NAYUDU.DASARADHI SITA VINOD
B.Tech (Hons.) Electrical & Electronics
Engineering
Eturu,
chandhralapadu (mandala),
Krishna (Dist.),
A.P
E-mail: *********@*****.***
Contact No: 895*******
CAREER OBJECTIVE:
To work in a firm with a professional work driven environment where I can utilize and apply my knowledge, skills which would enable me as a graduate to grow while fulfilling organizational goals.
CAREER SUMMARY
Having experience on Soc DESIGN AND VERIFICATION
Currently Working at Maven Silicon Pvt.Ltd at Bangalore as Intern.
Hands on experience in developing AHB-APB && AXI && SPI PROTOCALS.
Good knowledge of Verilog && System Verilog && UVM.
EDUCATIONAL QUALIFICATIONS:
S.No
Degree
Stream
School/
College
Board/
University
Year of Study
Aggregate 1.
B.Tech
EEE
VITAM
JNTUK
2010-2014
68
2.
Intermediate
MPC
Narayan Junior College
Board of Intermediate Education
2008-2010
90
3.
SSC
Apollo English medium school
Board of
Secondary Education
2007-2008
73.40
SUMMARY OF QUALIFICATIONS:
Good understanding of the ASIC and FPGA design flow.
Extensive experience in writing RTL models in Verilog HDL and Test benches in System Verilog and UVM.
Very good knowledge in verification methodologies.
Experience in using industry standard EDA tools for the front-end design and verification.
TB Methodology: UVM,SV,VERILOG
Protocols: UART, SPI
EDA Tool: Questasim and ISE
PROFESSIONAL SKILLS:
Technical Skills
Universal Verification Methodology(UVM)
System Verilog(SV)
Advanced Verilog
Verilog(EDA tool-Xilinx, Questasim)
Digital Design
Software Skills
C
MS-Office
TECHNICAL PROJECTS:
PROJECT-1: Router1x3-RTL design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description:
The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL.
Architected the class based verification environment using system Verilog
Verified the RTL model using System Verilog.
Generated functional and code coverage for the RTL verification sign-off
PROJECT-2: SPI Controller Core - Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Questasim
Description:
The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off.
PROJECT-3: AHB2APB Bridge design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tool: Questasim
Description:
The AHB to APB Bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL
Architected the class based verification environment in UVM
Verified the RTL module with single master and single slave
Generated functional and code coverage for the RTL verification sign-off.
PROJECT-4: BUCK BOOST CONVERTER
Description:
DC-DC conversion used in industries to supply different power levels to different machines
CO-/EXTRA-CURRICULAR ACTIVITIE
NSS (National Social Service) volunteer during Graduation
ACHIEVEMENTS
Won a second prize in chess in JNTU-Kakinada inter college sports meet in year 2012.
INTERPERSONAL SKILL
Ability to rapidly build relationship and set up trust.
Confident and Determined
Ability to cope up with different situations
PERSONAL DETAILS
Father’s Name :- Nayudu.Kaleswara rao
Permanent Address :- Eturu, chandhralapadu (mandal),Krishna(Dist.),A.P.
Date of Birth :- 06thJune 1993
Language Known :- English & Hindi & Telugu
Marital Status :- Single
Nationality/Religion :- Indian / Hindu
Interest & Hobbies :- Internet browsing,reading books, swimming
DECLARATION
I do hereby declare that the above information is true to the best of my knowledge.
Place: Vinod
Date: (Signature)
Contact this candidate