Engineering Design

Edwin Garcia

**** *** **** ****** ● San Jose, CA 95131● 408-***-****●************@*****.***

OBJECTIVE: To seek an entry level software/hardware engineering position

EDUCATION: Major: Bachelor of Science – Computer Engineering GPA: 3.57/4.00

San Jose State University, CA -Expected Graduation: May 2016

RELEVANT COURSEWORK: C programming, C++, Digital Design, Data Structure, Microprocessor Design, Advanced Algorithms, Computer Architecture and Design, Operating Systems, Databases

RELEVANT WORK EXPERIENCE

Landscaper, Garcia Garden Service, Santa Clara, CA January 2008-Present

-Managed a group of 3 people to complete a 7-day project in 5 days

-Handled transactions of up to $2,000

-Introduced a time-efficient plan that reduced labor time by 15 percent

-Increased revenue by bringing in projects ranging from $60 to $200

Software Development Internship, Intel Corporation, Hillsboro, OR Summer 2014

-Created and revised Validation Tests, in C, for the IPMI Utility tool that’s being used within ORCM (Open Resource Cluster Manager)

-Wrote a 9 page document detailing the steps for the IPMI Validation Tests for a group of 9 people

Software Development Internship, Intel Corporation, Folsom, CA Summer 2013

-Wrote basic Unit Level Tests in Linux

-Generated and installed new certificates successfully 30 percent faster

Intel Ultimate Engineering Experience, Intel Corporation, Santa Clara, CA Summer 2012

-Collaborated with a group of 6 to assemble and program a quad copter that flew for 5 seconds

-Presented a solution on a given engineering problem to an audience of about 50 people

-Designed and programmed a computer game, using C#, that came in 4th place out of 10 groups

PROJECTS -Used C++ to create a virtual bank account with features such as deposit, withdraw, and CD account

-Used Verilog language to design a small calculator in Xilinx IDE Design Suite and loaded it onto the FPGA Nexys2 board

-Extended the functionality, of a given Verilog source code that simulated a single cycle processor, to include more instructions and then modified the Verilog source code to simulate a Pipeline MIPS processor

-Implemented/Created a microprocessor system, using the LPC1768 processor, that interacted with different interfaces, such as the DS1306 Real-Time Clock, TSOP1236, and the AT45 Serial Flash Memory

-Currently working on Senior Design Project that is intended to be an interactive speaker comprised of a Raspberry Pi 2, a database using MySQL, and custom circuitry to display audio

QUALIFICATIONS -Strong fundamental understanding of C/C++ principles

-Experience in writing C/C++ in a collaborative coding environment using GitHub

-Familiar with Verilog HDL and Digital Design

-Effective communicator and works well with others in a team environment

-Hard and responsible worker, quick learner, and comfortable with leadership roles

SKILLS

Technical: C/C++, Verilog HDL, Nexys2 FPGA Board, MIPS Assembly Language, x86 Assembly, RTL Analysis, ISE Design Suite, Eclipse, GitHub, Microsoft Visual Studios, Google C++ Testing Framework, Linux/Unix, SQL

Recognitions: 2014-2015 Dean’s Scholar, 2013-2014 Dean’s Scholar, Intel Recognition Award

Languages: Spanish

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