Project Engineer
Resume:
MD ZAHEER
Madanapalle, Chittoor Dist, AP
**********@*****.***
Mobile Number: +91-949*******
Telephone Number: 08571- 227388
CAREER OBJECTIVE:
To work in pragmatic way in an organization, where I can show my talent and enhance my skills to meet company goals and objective with full integrity and zest
ACADEMIC QUALIFICATIONS:
M.Tech ( VLSI) - JNTU Kakinada - 80.10%
B.Tech ( E.C.E) - Sree Vidyanikethan Eng College - 79.85%
INTERMEDIATE - Narayana Jr College - 91.40%
S.S.C - Gnanodaya High School - 92.67%
ACHIEVEMENTS:
• Secured II prize in GLITTER THE LITTER Fest held at
SVEC on 27th March, 2011.
• Secured III Prize in Indian Student Technical Association(
ISTE) on 23rd Nov, 2011.
• Secured III prize in the INTERNATIONAL CARNIVAL held at
VIT UNIVERSITY on 18th September, 2011.
EXPERIENCE:
Tata Communications Ltd: GET
[Jun 2013- Oct 2013]
• Designed more than 65 orders in NGP Access Planning Team.
Performed Time bound tasks and High priority orders. Gained
experience with a wide variety of People and work culture.
Electronics% Corporation of India Ltd( ECIL):GEA
(Nov 2014 - Nov 2015)
• Designed Projects for ONGC, BHAVINI, BHEL using E- Plan Electric P8 and hands on Experience on EVM's debugging and Hardware Modelling.
CORE COMPETENCIES:
Project 1:
• Design and Functional verification of VLSI based Router 1X5
Architecture in Verilog modelling using Xilinx ISE simulation
tool.
Project 2:
• Designed Two Port Arbiter using System Verilog and Verified
using Layered Test Bench Architecture during 2nd Semester of
M.Tech.
Project 3:
Black Box Testing at BEL, Bangalore.
• Embedded system for Black Box Testing at BEL
( Bharat Electronics Limited), Bangalore.
Design and Implemented using PIC16F877A and Embedded C.
Role: Team Leader.
Project 4: Design Engineer at Tata Communications, Chennai.
• Designed Electronic circuits( IPVPNQOS, EWL, DSL) by
intervening ports and capacity of Mux and Routers using
OSME, Cramer at TCTS, Chennai.
Project 5: SCAP for ONGC Petro Additions, Dahej, Gujarat.
• Designing Schematics and Assembling through Functional Testing using E- Plan.
Project 6: PLC Based TA Examination of Panels, Bhavini, Chennai.
• Designing and Assembling of Annunciation Panels through Functional Testing.
TECHNICAL SKILLS:
• Languages
Verilog, System Verilog, Universal Verification Methodology
( UVM), C, OOPS, HSPICE, Basics of Perl and Python.
• Tools
E- Plan Electric P8, Auto CAD, Design Compiler, IC Compiler,
Microwind, ARMSim, Networking, Routing, Synchronous Digital Hierarchy( SDH).
COYCURRICULAR ACTIVITIES:
• Organized Association of Communication Majors and Enthusiasts( ACME) in Planning Committee during the year 2010-2012.
• Participated in ROBOTICS, NANOMATERIALS WORKSHOP held at IIT MADRAS on 29th September, 2011.
• Participated in Poster Presentation, held at K.L UNIVERSITY
on 14th Oct, 2011.
• Participated in Paper Presentation held at S.V UNIVERSITY
on 28th January, 2012.
STRENGTHS:
• Diligence, Gregarious Person, Friendly Nature.
HOBBIES:
• Philatelist, Numismatist. Surfing Internet.
PERSONAL INFORMATION:
Name : MD Zaheer
Father's Name : S. Kaleem Basha
Date of Birth : Feb 12, 1992
Known Languages:: English, Hindi, Telugu, German( Beginner)
DECLARATION:
I here by declare that the information furnished above is true to the best of my knowledge.
Date:
Place: ( MDZAHEER)
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