Design Engineer Driver

Henry H. Yuan

Seeking an Analog/ Mixed or Power Management Integrated Circuit(PMIC) Design engineering position with interested in: DC/DC converter including switching regulators, Step up regulators (Boost), Step down regulators (Buck), Inverting regulators (Buck-Boost) and Linear Regulator

Master of Science in Electrical Engineering (November, 1998)

The Pennsylvania State University, University Park, PA

Bachelor of Science in Physics (June, 1992)

National Sun Yat-Sen University, Kaohsiung, Taiwan

Non-linear Slope Compensation for pulse width modulation current mode control (Individual Inventor, US8138740 B2 October 2012)

Integrated Soft Start (Co-Inventor, US20090174385 A1 November 2013)

Digital Soft Start With Continuous Ramp-up (Lead Inventor, US20140266397 A1 Sep 18, 2014)

Duty Cycle Dependent Compensation Slope for Current Mode Switching Regulator (Lead Inventor, US20140266110 A1 Sep 18, 2014)

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Cadence Virtuso ADE-L, ADE-XL, HSPICE, SPECTRE, SIMetrix/SIMPLIS, VerilogD, VerilogA, UNIX, LINUX, Oscilloscope, Curve tracer, Active load, Function generator etc. PC software utilities: word processing, spreadsheets, Microsoft Office and Visio

EXAR Corporation. Fremont, CA (July, 2014 - July, 2015)

Staff Analog Design Engineer

Design IPs for 5V-22V Two Phase Buck PWM Module or controller, XR791xx, (EXAR Patented Architecture, V2 control), with PLL frequency control, Dual 13A or Single 26A Output (TSMC 0.18µm+LDMOS)

oDesign a low frequency (400KHz -780KHz) PLL for switching control

oDesign and simulation on bootstrap driver with non-overlap delay

oDesign low side current limit, high side current limit and high voltage high side current sensing

oSIMPLIS simulation verification for architecture and application conditions

oTop level simulation verification for applications with current sharing for two phase module

oGenerate test and trim table

Design bootstrap driver for 5V-22V, Buck control Module (TSMC 0.18µm+LDMOS)

oDesign and simulation on bootstrap driver with non-overlap delay for controller with Power MOSFET and DrMOSs

oTop level simulation verification on load/ line regulation for applications

SanDisk Corporation. Milpitas, CA (May, 2010-July, 2014)

Staff Analog Design Engineer

2.5V ~ 5.5V 2.0MHz Current Mode BUCK Switching regulator IP for PMIC, output = 0.8V – 2.2V, up to 3.0A (Individual Design Project, TSMC 0.18µm, Test bench validated, Production)

oProduct Definition, generated product specification and application data sheet

oArchitecture, design from scratch to build schematics and simulations for PMOS and NMOS switch, non-overlap switch drivers, error amplifier, PWM comparator, capacitor multiplier, summation block, artificial ramp, non-linear slope compensation, level shift, pre-driver and current sensing. PVT and Monte Carlo simulations

oInternal continuous digital soft start, oscillator, pre-regulator

oCycle by cycle current limit and skip mode

oPower dissipation estimated for metal routing

oTest plan and evaluation board review

2.5V ~ 3.6V 2.0MHz Current Mode BUCK Switching regulator IP, output = 0.8V – 2.2V, up to 1200mA (Individual Design Project, TSMC 40nm, Test bench validated, Production)

oProduct Definition, generated product specification and application data sheet

oArchitecture, design from scratch to build schematics and simulations for PMOS and NMOS switch, non-overlap switch drivers, error amplifier, PWM comparator, capacitor multiplier, summation block, artificial ramp, non-linear slope compensation, level shift, pre-driver and current sensing. PVT and Monte Carlo simulations

oInternal continuous digital soft start, oscillator, pre-regulator

oCycle by cycle current limit and skip mode

oPower dissipation estimated for metal routing

oTest plan and evaluation board review

2.5V ~ 3.6V 10.0MHz Voltage Mode BUCK Switching regulator test chip, output = 0.8V – 2.2V, up to 800mA (Individual Design Project, TSMC 40nm, Test bench validated)

oDesign Target Definition, generated product specification and application data sheet

oArchitecture, build schematics and simulations for PMOS and NMOS switch, non-overlap switch drivers, error amplifier, PWM comparator, capacitor multiplier, artificial ramp, slope generator, level shift, pre-driver and current sensing

oInternal continuous digital soft start, oscillator, pre-regulator

oCycle by cycle current limit and skip mode

oPower dissipation estimated for metal routing

oTest plan and evaluation board review

Analog IPs and Test Chips: Linear Regulator, Core Regulator, Capless Regulator Oscillator, Operational Amplifier, OTA, voltage and current references and test control (TSMC65nm, TSMC40nm, TSMC 28nm, UMC65nm, UMC40nm, SMIC55nm)

IML, Inc. Campbell, CA (October, 2003 – May, 2010)

Senior Analog Design Engineer • Analog Design Engineer

IML8934 Falcon3-lite, multi-channel, design 8.0V ~ 12.0V input 3.8A 1.0MHz LDNMOS switch asynchronous current mode boost(step up) regulator, output up to 20V and 8.0V ~ 12.0V input 2.0A PMOS switch asynchronous current mode buck-boost(inverting) regulator, output up to -24V for this multi-channel power management IC (UMC 0.35µmCMOS technology with LDMOS)

oLDNMOS switch for boost, HV PMOS switch for buck-boost, error amplifier, PWM comparator, capacitor multiplier for buck-boost, summation block, artificial ramp, non-linear slope compensation, level shift, pre-driver, and current sensing

oInput feed forward, external adjustable soft start, internal digital soft start, oscillator, pre-regulator, BANDGAP, UVLO, thermal shutdown

ocycle by cycle current limit, skip mode, short circuit protection and over voltage protection

IML8933 Multi-channel, design comment blocks and 2.5V ~ 5.5V input 2.0A 1.0MHz, LDNMOS switch asynchronous current mode boost(step up) regulator, output up to 16V for multiple channel power management IC (UMC 0.35µmCMOS technology with LDNMOS)

oLDNMOS switch, error amplifier, PWM comparator, summation block, artificial ramp, non-linear slope compensation, level shift, pre-driver, and current sensing

osoft start, oscillator, pre-regulator, BANDGAP, UVLO, thermal shutdown, cycle by cycle current limit, skip mode, short circuit protection in hiccup mode and over voltage protection

oindividual design non-linear slope compensation with patent filed pending for this design

IML8811 2.5V ~ 5.5V input 1.6A 1.2MHz, 650KHz LDNMOS switch asynchronous current mode boost(step up) regulator, output up to 16V (Individual Design Project, UMC 0.35µmCMOS technology with LDNMOS)

oLDNMOS switch, error amplifier, PWM comparator, summation block, artificial ramp, level shift, pre-driver, and current sensing

oInternal soft start, oscillator, pre-regulator, BANDGAP, UVLO, thermal shutdown cycle by cycle current limit, skip mode and over voltage protection

IML79xx 2.5V ~ 5.5V input 2.4A HV NMOS 1.2MHz, 650KHz asynchronous current mode boost(step up) regulator, output up to 16V (Individual Design Project, UMC 0.35µmCMOS technology with High Voltage MOS)

oHV NMOS switch, error amplifier, PWM comparator, summation block, artificial ramp, level shift, pre-driver, and current sensing

oexternal adjustable soft start, oscillator, pre-regulator, BANDGAP, UVLO, thermal shutdown cycle by cycle current limit and skip mode

2.5V ~ 5.5V Multi-channel, design voltage mode boost(step up) and buck-boost(inverting) controllers for seven channel DSC(Digital Still Camera) power management IC (Vanguard 0.5µm technology)

1.6A current mode asynchronous boost(step up) controller verification and debugging

National Semiconductor, Inc. Sunnyvale, CA (November, 1998 – September, 2003)

Sr. Circuit Design Engineer • Design Engineer

Compiler SRAM design Dual port SRAM, DRAM, RS CAM

oDesign Decoder, Sense Amplifier, State Machine, Memory Control Logic

oVerilog Modeling for memory, Run LVS and DRC for memory compiler

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