vlsi design verification engineer
Resume:
Vinod Kumar
Gurgaon, *22011
Mob: +91-875*******
E-mail: *********@*****.***
Objective
To work with an organization offering challenges and growth with opportunities to enrich my knowledge and skills while contributing my best to the organization I work for.
Experience
Working as an Intern for Xinoe System Pvt. Ltd. Gurgaon since June-1-2015 to Nov-30-2015.
Professional Summary
Good understanding of ASIC flow.
Good understanding of Logic Design, System design using HDL.
Good Understandings about Verification Environment, Test cases, Test Benches, RTL and Gate level Verification.
Good Understanding of FPGA Design.
Good Understanding of C, C++.
Technical Proficiency
Skill Summary Design Tools Knowledge:
HDL Language : Verilog
HVL Language : System Verilog
Scripting Language : Perl
Tools : Xilinx, Modelsim, Questasim.
Methodology : UVM
Operating System : Linux, Windows
Protocols : AHB, I2C.
WORK EXPERIENCE
Project : 1
Organization : Xinoe system pvt ltd
Duration : 1 Month
Name : AHB2WISHBONE Bridge
HVL : System verilog
Role : Written Test cases for checking read,
Write and read after write case data Transfer.
Tools : Questasim
Project : 2
Organization : Xinoe system pvt ltd
Duration : .5 month
Name : Verification of FIFO
HVL : System verilog
Methodology : UVM
Role : Written test cases for half duplex and full duplex transfer.
Tool : Questasim
Project : 3
Organization : Xinoe system pvt ltd
Duration : .5 month
Name : Verification of AHB MASTER and AHB MULTIPLE SLAVE
HVL : System Verilog
Methodology : UVM
Role : Created environment, written various test cases
And finding coverage report
Tool : Questasim
Project : 4
Organization : JB Tech India
Duration : 2 Month
Name : Alarm clock Design & FPGA implementation
HVL : Verilog
Role : Written RTL code in verilog for clock and implemented it on FPGA.
Tool : Xillinxs ISE design tool.
Project : 5
Organization : JB Tech India
Duration : 1 Month
Name : One-way Traffic light controller design & FPGA implementation
HDL : Verilog
Role : Written RTL as per Design Spec.
Tool : Xilinx.
Project : 6
Organization : JB Tech India
Duration : 1 Month
Name : Clock gated low power sequential circuit design of ALU.
HDL : Verilog
Role : Written Behavioral model in Verilog.
Tool : Xillinxs.
Project : 7
Organization : JB Tech India
Duration : 1 Month
Name : FIFO.
HDL : Verilog
Role : Written Behavioral model in Verilog.
Tool : Xillinxs.
.
B.Tech with 71.46% from Uttar Pradesh Technical University (20011-2015).
VLSI Design Course from Jb tech India gr noida (Jun 2014- Dec 2011) .
STRENGTHS
Strong logical problem solving approach.
Positive, Confident and motivated.
Adaptive to change.
Achievements
Organized a workshop of VLSI in Delhi University.
Participated in workshop on Ethical Hacking organized by Kyrion
Extra Curricular Activities
Participated in state level Basket Ball Championship
1st prize in wrestling & kabbadi in college sports day.
2nd Prize in weight lifting in college sports day.
Weakness
I can’t say no when someone ask for help.
Personal Profile
Name : Vinod Kumar
Marital Status : Single
DOB : 25-Nov-1993
Nationality : Indian
Languages known : English, Hindi
Declaration
I hereby declare that the above information given by me is true to the best of my Knowledge.
Date: Place: Gurgaon
Vinod Kumar
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