Engineering Design

B.MANIKANDAN No: */***, Middle street,

G.Ariyur & (post),

Thirukoilur (Tk),

Villupuram (Dt)-605751

***********@*****.***

Cell No: 967-***-****

Objective

To work for an organization which provides me the opportunity to improve my skills and knowledge to growth along with the organization objective.

Education

Name of Examination

Institution

Board

Percentage of Marks

Year of Passing

M.E(VLSI Design)

Sri Venkateswara College of Engineering and Technology

Anna university

86(with Distinction and University 33rd Rank holder)

May-2014

B.E (ECE)

Dr.Navalar Nedunchezhiyan College of Engineering

Anna University

81

April-2012

HSC

A.V.N.C Govt.Hr.Sec School, G.Ariyur.

State Board

69

March – 2008

SSLC

A.V.N.C. Govt. Hr.Sec.School, G.Ariyur.

State Board

76

April – 2006

Computer Skill Set

Languages : VHDL,Verilog,C,C++.

Operating Systems : Windows 2000/XP, Windows 7.

Electronic Software Tools :ModelSim,QuatrusII&Xilinx, MATLAB,PSPICE,Tanner.

Certificate Course :DCA,ADCHN.

Area of Interest

Digital Electronics

VLSI Design Technique

Testing of VLSI

Industrial Training

Undergone Inplant Training at,

(BSNL)BHARAT SANCHAR NIGAM LIMITED-Villupuram during JUNE 2010.

VI MICROSYSTEMS PVT.LTD.,-Chennai during OCTOBER 2010.

PROJECT

Project in M.E:

Title : Design and Implementation of Testable Reversible Sequential Circuits

Duration: 6 Months.

Tools : Model Sim, Xlinix

Language : Verilog, VHDL

Synopsis : The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip flops and latches. The conservative logic gates are Feynman, Toffoli and etc., The conservative logic gates are in terms of complexity, speed and area.

Project in B.E:

Title : Low Power Address Generator for MBIST

Duration : 6 Months.

Tools : Model Sim

Language : Verilog, VHDL

Synopsis : Memory Built-in Self-Test (MBIST) is used to test embedded memories. Many algorithms were developed for MBIST, but few of these techniques focus reducing the switching activity in the address bus. The switching activity is proportional to the test power.

Extra Curricular Activities – Awards and Achievements

Participated in the Special Camp for the Bharath Scouts & Guides.

Got best student award in my School.

Co-Curricular Activities

International Conferences:

Participated and presented a paper on “Design and Implementation of Testable Reversible Sequential Circuits” in the International conference on Electrical, Communication & Computing-2014 organized by Tagore Engg College, Chennai.

Participated and presented a paper on “Design and Implementation of Testable Reversible Sequential Circuits and Garbage Output” in the International conference on TITCON-2014 organized by AVS Engg College, Salem.

National Conferences:

Participated and presented a paper on “Power Optimized Address Generator For Memory Build In Self Test” in the National conference on Signal Processing & Communications-2012 organized by St. Peters college of Engineering and Technology, Chennai.

Participated and presented a paper on “Performance of Universal LDPC Codes Under Faulty Iterative Decoding” in the National conference on Research Trends in Electronics & Communication-2013 organized by St. Joseph college of Engineering, Chennai.

International Journals:

“MBIST & ULDPC” Paper published on June 2012 in ‘International Journal of Advanced Scientific and Technical Research’.

“Design and Implementation of Testable Reversible Sequential Circuits Optimized Power” paper published on Feb 2014 in ‘IJCER’.

National Journal:

“FSM based MBIST” Paper published on Oct 2013 in ‘Quest Journals’.

Workshop & Seminars:

Participated and presented a paper on “Nano Technology” in the National Level Technical Symposium on Electronics & Communication Engineering-2011 organized by Cauvery College Of Engineering & Technology, Trichy

Participated in the one day workshop on “Embedded Systems” at Jayaram College of Engineering and Technology-2010.

Participated in the one day workshop on “ADIP” at Kumaraguru College of Technology-2010.

Participated in the two day FDP on “VLSI Design flow tools and LABVIEW based system design” at Aalim Muhammed Salegh College of Engineering-2012.

Personal Profile

Father’s Name : N.BOOPATHI

Date of Birth : 26.06.1991

Gender : Male

Nationality : Indian.

Languages Known : English, Tamil.

Hobbies :Playing Games and Internet.

Declaration

I hereby declare that all information given above is true and correct to the best of my knowledge and belief.

PLACE :G.Ariyur (B.MANIKANDAN)

DATE :

Contact this candidate