Microsoft Office Power

R S G BHAVANI E-Mail : *******.***@*****.***

Mobile: 898-***-****

To secure a challenging position where I can effectively contribute my skills and derive utmost job satisfaction.

SUMMARY

Experience in working with Mentor graphics (Pyxis) tool in designing schematic and layouts (LVS and DRC) for digital circuits on different technology files( Tsmc 40nm, 16nm).

Experience in designing digital circuits by using Tanner EDA Tool and Hspice (synopsys).

Worked on VHDL language on XILINX platform.

Experience working with MS office Suite (Word, Excel, Access and Power point skills).

Participated in IEEE Section Student Congress & All India Student project Contest 2009 held at Hyderabad.

Worked as an IEEE and WIE (Women in Engg) volunteer for 2 years at pydah IEEE student branch.

Excellent communication, presentation, analytical and problem solving skills.

ACADEMICS

M.Tech – VLSI and Embedded System from GVP college for women (JNTU Kakinada), December 2014, with 72.07 percentage.

B.Tech- Electronics and communication engineering from Pydah college of engg and technology (JNTU Kakinada), 2012, with 75.36 %.

Intermediate, Board of Intermediate education (Andhra Pradesh), 2008,with 90.9%.

CBSE class 10th, Kendriya vidyalaya, Visakhapatnam (India), 2006, with 71%.

TECHNICAL SKILLS

Applications : Microsoft office ( Word, Power point, Excel, Exchange).

Programming Languages: C, VHDL, Verilog

JAVA, PSPICE, and MATLAB as part of academics.

TOOLS: Modelsim, Tanner EDA, HSPICE, MENTOR GRAPHICS (PYXIS), LVS and DRC.

ACADEMIC PROJECT

Low power and high performance VLSI interconnects by Schmitt trigger technique in Nanoscale regime

In DSM, the delay offered by the interconnect is more than the gate delay. To reduce the interconnect delay we used the buffered and Schmitt trigger Techniques.

Tools: Mentor graphics, H-spice

Technology: 180nm, 90nm,65nm,and 45nm.

Supply voltage: 1.8V

Design of Low Power CMOS Circuits in Nanoscale Technology

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence static power dissipation. Hence to reduce static power without effecting Dynamic power we used a technique called LECTOR.

Tools: Tanner EDA and H-spice

Technology: 180 nm, 90nm,65nm,45nm.

Supply voltage: 1.8V

●Industrial Project( Hindustan Shipyard Limited, Visakhapatnam)

Communication Equipment and Navigation systems in on-board ship

We worked on the project which deals with the various communication equipments used for communication in ships.

PUBLICATIONS

Published a paper on “Leakage Power Reduction In CMOS Circuits Using Leakage Control Transistor Technique In Nanoscale Technology” in International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-2 Iss-1, 2012.

Published a paper on “Low Power and High Performance VLSI Interconnects By Schmitt Trigger Technique In Nanoscale Regime”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Vol. 4 issue 5, 2014.

PERSONAL DETAILS

Name : R Santoshi Ganga Bhavani

Father’s name : R Yeriki Naidu

Date of birth : 17 December 1990

Hobbies and interests : listening to music, Cooking, web surfing, playing outdoor Games

Strengths : Quick learning, Self motivation, positive thinking

Languages known : English, Hindi, Telugu

Address for communication: DR NO.39-8-77/2/1, Balaji plaza

Muralinagar, industrial estate post

Visakhapatnam-530007

DECLARATION

I hereby declare that the above information provided by me is true to the best of my knowledge and belief.

PLACE: Visakhapatnam SIGNATURE

DATE: 09-11-2015 (R S G BHAVANI)

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