Design Engineering

KAPA KEHARIKA

K.KEHARIKA

Email: *.********@*****.***

Contact No: 970-***-****

CAREER OBJECTIVE

To be a part of a company that provides professionally dynamic environment where I can utilize my intellectual and problem solving skills for the development of company.

ACADEMIC REVIEW

M.Tech in VLSI SD(2013-2015) from JNTUA University with an aggregate of 83.3% (up to First year).

B.Tech(E.I.E) in 2012 from LAKIREDDY BALIREDDY COLLEGE OF ENGINEERING (JNTUK) with an aggregate of 72.9%.

Intermediate (M.P.C) in 2008 from S.V.R.G.N.R COLLEGE( Board of Intermediate), AP with an aggregate of 88.2%.

SSC in 2006 from Z.P.G.H.SCHOOL (SSC), AP with an aggregate of 82.5%.

TECHNICAL PROFILE

Languages : Verilog, Perl.

Simulator tools : VCS,H-SPICE.

Synthesis tools : DC compiler, IC compiler.

AREA OF INTEREST

Digital VLSI Design

Verilog HDL

ACHIEVEMENTS

A Presentation on VIRTUAL INSTRUMENTATION and got first prize in event conducted by SIR C.R.REDDY COLLEGE OF ENGINEERING.

Presented a technical paper On PILL CAMERA in SWARNA BHARATHI COLLEGE OF ENGINEERING.

Participated in work shop on Robotics conducted by KAKATIYA INSTITUTE OF TECHNOLOGY.

ACADEMIC PROJECT

M.Tech MAJOR PROJECT:

An efficient method for reducing leakage power in vlsi design:

Portable electronic devices are integral components in our daily life. Even though the devices are not in active use, there is a leakage power consumption with downward scaling of technology. So there is need to reduce leakage power consumption, for that we are proposing a method called stacked sleep transistor technique and also going to analyze for different logic circuits by using PDK 90nm technology. This approach is going to analyze over existing methods like Sleep Transistor Technique, Sleepy Stack Technique and Sleepy Keeper Techniques such that we are going to reduce leakage power and power delay product. So that device performance is going to increase.

Tool : Cadence 4.1 v

Technology : 90nm

Tool for Layout and Verification : Cadence Virtuoso & Diva.

M.Tech MINI PROJECT:

Design of shift register:

Shift Registers are generally used to convert serial data to parallel data. The RTL is designed and simulated using Synopsys Verilog compiler simulator (VCS).

Design and Verification of counters:

RTL code for counters are designed and verified using Synopsys VCS.

Design and verification of ALU:

ALU is part of CPU which is used to carry arithmetic operations such as addition, subtraction, multiplication, division, AND, OR, NOT, Comparison and many more. The RTL code for an ALU is designed and verified using Synopsys VCS Tool.

PERSONAL DETAILS

Address : D.NO:4-25, KUMMARI STREET,

MYLAVARAM,KRISHNADISTRICT,A.P.

Date of Birth : 13 June 1991

Nationality : Indian

Languages Known : English, Telugu

DECLARATION

I hereby declare that all the details provided are true to the best of my knowledge.

Place : Hyderabad K. Keharika

Date:

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