Design Project

Gunda Vishnu

Mobile: 809-***-****.

Email:*******.**@*****.***

Objective:

To obtain analog design engineering position to utilize my knowledge of circuit design in areas of analog and digital as well as control and power electronics. Willing to relocate.

Experience:

Academic Work:

Designed CMOS transistor-level analog blocks OpAmp, Bandgap References, comparator, I/O circuits, ADC and DAC. The design effort included system level design flow, schematic capture, simulation and IC layout (DRC and LVS) using Cadence Virtuoso.

Designed transistor level integrated circuit block – Full Adder. The design effort included PSPICE simulation and CMOS Layout using L-EDIT. Area Specialization:

Digital Logic Design, ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place & Route, Timing Verification, EDA Tools & Computer Architecture.

Skills/Tools:

Hardware Description Language: VHDL.

Design Tools: Spectre, SPICE, HSPICE.

EDA Tools: Cadence, Tanner, Synopsys, Magic.

Languages: C, Python, Perl.

Operating Systems: Windows, UNIX.

EDUCATIONAL QUALIFICATION:

• M.Tech (VLSI) with aggregate 66% in Gitam University (2013-2015).

• B.Tech (Electronics and Communication Engineering) with aggregate 63% from JNT University, Hyderabad (2008-2012).

• 12th with aggregate 80% from Excellent Junior College in 2008.

• 10th with aggregate 87% from Pragathi High School (S.S.C) in 2006. STRENGTHS:

• Determined to learn with practical approach.

• Thinking easy way of Solving Problem.

Project Profiles:

Tool Used: Cadence

Role: Individual

Project-1: Leakage Power Reduction for Domino Circuits in 45nm CMOS Technologies.

Description :

A circuit for reducing both the subthreshold and gate oxide leakage power in the domino logic circuits. Three high-Vt sleep transistors are added to the standard domino logic circuit to place the circuit into low leakage state. Circuit is evaluated at 110 C and 25 C. At 110 C, circuit reduces leakage power consumption by up to 63%, and at 25 C, it reduces by up to 95.3% as compared to standard dual-Vt domino circuits. Similarly, this circuit reduces leakage power consumption at 110 C by 83.5%, and at 25 C, it reduces up to 95.7% as compared to standard low- Vt domino circuits.

Project-2: Implementation of Bandgap Reference Circuits. Description:

In the design of analog integrated circuits it’s important to create reference voltages and currents with well defined values. Bandgap reference circuits are regularly used to achieve it on-chip. Especially in analog to digital conversion, where the input voltage is compared to several reference levels in order to determine the corresponding digital value, a best application is this bandgap reference voltage. The main intention in this project work is to understand the performance limitations as well as the design of a bandgap reference circuit, BGR. In this project work we studied the different types of bandgap reference types and bandgap circuits. Then a detailed analysis of Opamp design was studied. Finally the BGR circuit which is capable of producing an constant output reference voltage for given supply voltage was implemented .The tool used is CADENCE for simulation and all of these circuits are implemented in 90nm standard CMOS technology.

PERSONAL DETAILS

Name : Gunda Vishnu

Date of Birth : 14-05-1991

Sex : Male

Marital Status : Single

Languages known : English, Telugu

Permanent Address : 4-2-58\1\1, Mahabubabad, Warangal. Hobbies : Playing Video Games, Chess, and Cricket. DECLARATION:

I hereby declare that all the above information provided by me is true and correct to the best of my knowledge and belief.

DATE:

PLACE: GUNDA VISHNU

Contact this candidate