Senior Hardware Engineer

JOHN EDWARD DEAN

**** ****** ******* ***, *** Diego, CA 92130

845-***-**** ~ *********@*****.***

CAREER SUMMARY:

Senior Hardware Research Engineer and Prototype Group Team Leader with extensive experience in cutting edge hardware design and architecture in applications including medical ultrasound, HDTV, research displays, wireless lighting systems, and defense electronics. The go-to hardware guy on virtually every project over the last 20+ years. Focused, high adrenaline leader and worker who learns new tools and application domains quickly and genuinely enjoys working on projects end-to-end including detailed requirements, design specifications, architecture, circuit and system design, simulation, and debug/integration. Comfortable starting a new project, working within the confines of an ongoing project, or rescuing troubled projects. Works well in team environment or independently. Strong software and analog skills. Very strong written and strong oral skills. BS/EE, MS/EE.

SKILLS/EXPERIENCE:

FPGA used: Altera Cyclone III, IV, V, Stratix II, IV, MAX II, 10K series. Xilinx Virtex 4, Spartan, 4000 series, 3000 series

FPGA tools: Altera Quartus, Qsys, Aldec, Modelsim, Xilinx ISE, Synopsys, Synplicity, Static Timing

Software tools: Visual Studio, Source Insight, Matlab, Eclipse, various compilers

Schematic Capture: Orcad, Mentor, Future Net, others

High Speed Board Design: Howard Johnson courses

Languages: VHDL, some Verilog, C, PL/M-51, Pascal, assembly, BASIC, FORTRAN

Processors: NIOS II, Ember EM250, 8051, 80C31, 68000, TI9900, 8080

Buses/Interfaces: Avalon, USB-3, USB-2, PCI, VME, SPI, IIC, RS-232, RS-485, LVDS, proprietary

Memories: DDR2,3, LPDDR2, Serial/Parallel Flash, SDRAM, SGRAM, SRAM, and others

Wireless: ZigBee

PROFESSIONAL EMPLOYMENT:

Philips Research Labs Senior Research Engineer and Group Leader 1991 to Present

Briarcliff Manor, NY. (Cambridge, MA beginning 9/2015)

Clinical Trial Acquisition System 2015 to Present

Developed architecture and firmware for an ultrasound clinical trial research prototype. System includes a PCB with a Cyclone V GX FPGA and LPDDR2 memory. Data streamed to PC via USB-3. Developed firmware including logic in VHDL, subsystem using Qsys, and embedded software in C for the NIOS processor. System is in process of regulatory approval. Next step is implementation of novel algorithms in the FPGA.

Advanced Ultrasound Research Prototype 2012 to Present

Developed architecture and firmware for an ultrasound research prototype platform design that is currently on a fast-track to a venture. System includes multiple PCBs, FPGAs (Altera Stratix IV and Cyclone IV), and dynamic high voltage switching of ultrasound signals. A key element of the system was the ability to stream ultrasound samples via USB-3. Delivered 3 other PCB prototypes based on this architecture platform. Two systems were purchased by a renowned university. Two other systems are in clinical trials in hospitals.

Doppler Ultrasound Research Prototype 2010 to 2012

Developed architecture and all FPGA (Cyclone III) firmware for a research ultrasound prototype targeted for emerging markets. System was successfully tested in clinical trials in India.

Intelligent Lighting System Using ZigBee 2008 to 2011

Developed a lighting system using ZigBee (Ember) wireless networks to control office lighting. Responsible for application layer microcontroller firmware in C and the architecture of all hardware. System included wireless light/motion sensors, ballast controls, and motor-controlled blinds. Test system was successfully deployed on an Army base in the Mojave desert and was used to collect data for a year.

Moonlighted: Part-Time Contractor on Xilinx FPGA Development for a Start-up 2008 to 2009

San Diego, CA

Development of Xilinx Virtex 4 firmware (VHDL) for an LCD interface to a signal processing chain. Implemented embedded PowerPC 405 environment and also designed shared memory interface using MPMC and VFBC modules.

Simulated an algorithm to dynamically measure the peak effective power of a signal processing circuit. Wrote testbench in VHDL to simulate several planned corner cases as well as others cases generated using constrained random inputs.

Development of Xilinx firmware to calculate an 8192 point FFT in real-time for a communications application.

Continued: Philips Research Labs Senior Research Engineer and Group Leader

Briarcliff Manor, NY

Ultrasound Acquisition Platform 2004 to 2008

Lead engineer and architect for development of an acquisition system to collect raw ultrasound samples from a commercial medical ultrasound machine. Eventually 4 of these systems were built and used by more than 10 projects over the last 10 years, contributing to new features, functions, business propositions, IP, and publications all related to Philips Ultrasound business.

This system acquired 32 GBytes of ultrasound into banks of DDR2 memories in 8 seconds over a distance of 3 meters using 128 LVDS pairs. Developed VHDL for Altera FPGAs/CPLDs. Among the challenges was the development of 4 memory boards in an industrial CompactPCI chassis. Another challenge was the design and integration of 16 daughterboards into a commercial ultrasound system without exceeding its power, temperature, and mechanical specs. Evolved custom variations of the acquisition system including one that used a laser to produce ultrasound in human tissue.

Liquid Crystal on Silicon (LCoS) Mixed Signal Display Chip 2003 to 2004

Lead hardware engineer for the digital portion of a liquid crystal on silicon (LCOS) display IC. Developed the architecture and implemented several modules including an embedded 8051. Developed boot loader in assembly. Wrote system functional test bench. Learned Synopsys scripting techniques to synthesize modules.

Liquid Crystal on Silicon (LCoS) Display Driver ASIC 2001 to 2002

Converted a research FPGA to an Altera Hard Copy ASIC implementation for the initial LCoS product release. Chip was successfully taped out and deployed in the first generation of the product. This driver chip was the basis for next generation architectures.

Liquid Crystal on Silicon (LCoS) Display Electronics Platform 1997 to 2002

Lead hardware engineer for a liquid crystal on silicon (LCOS) display system. Developed architecture and implemented FPGAs (Altera) for 5 generations of display driver hardware to implement remapping, scan conversion, control, and signal processing. Display was based on a novel single panel, scrolling color stripe technique that has been published in SID Journal, Elsevier, EE Times, and other publications. Based on research success, a business group was formed in 2000.

Digital TV Electronics 1995 to 1997

Designed a multi-processor board based on the Trimedia processor. Board consisted of an Altera 10K50 and 4 Trimedia TM1 chips. Designed electronics including Xilinx FPGA to control the pulsing of an experimental lamp for projection television applications. Co-developed architecture and specifications of HDTV MPEG-2 video decoder and display processor ASICs.

Grand Alliance HDTV MPEG-2 Video Decoder 1993 to 1995

Member of a team that designed an HDTV MPEG-2 video decoder rack. This was part of the FCC encouraged "Grand Alliance" effort to demonstrate an end-to-end HDTV terrestrial broadcast. Due in large part to our efforts, the FCC officially recognized ATV as the new US digital television standard in Dec/96. My responsibilities included the design of the System Control board and overall integration. The System Control Board consisted of 12 unique Altera CPLDs, 2 Xilinx FPGAs, PLDs, memories, and DSP.

Designed Inter/Intra Decision board for an HDTV encoder. Board consisted of 5 Xilinx FPGAs and assorted PLDs and memories.

Display Research 1991-1993

As a member of Display department, designed several circuits for control and/or processing of video signals for experimental LCD and DMD projection displays. Also simulated and analyzed many different video processing algorithms.

Bio Clinic Inc, Part-Time Contractor 1990 to 1991

Rancho Cucamunga, CA.

Responsible for all software (PLM-51) and some hardware design of a microprocessor (8031) controlled therapeutical air mattress bed for the medical market. The processor controls pressures within the mattress based on pressure transducer feedback. Product was successful in the market selling in the 1000s.

Philips Ultrasound Senior Hardware Engineer 1987 to 1991

Santa Ana, CA.

Designed production electronics and embedded software for a high end ultrasound imaging machine for the medical market including:

2D Doppler Board 1991

Designed board to measure blood velocity based on the Doppler shift of returning ultrasound echoes. Board consisted of AT&T DSP32C processors, Altera/Actel CPLDs, and memories.

Image Processing Board 1990

Designed an image processing board to interpolate and filter pixels from image memory in real time. Included 60 PLDs, 3 Xilinx FPGAs, 16 high speed PROMs, and a static RAM frame buffer.

Beamformer Controller Board 1988 to 1989

Wrote spec, designed and integrated the Beamformer controller board. Board consisted of PLDs and microsequencers and was used to control 17 other boards. Learned C in order to write my own drivers.

Human Interface Boards 1987 to 1988

Designed human interface board hardware and firmware including PLM-51 code for an 8031 microcontroller.

Texas Instruments Defense Electronics Group Senior Hardware Engineer 1979 to 1987

Dallas, TX.

TOW2 Missile Autotrack Program 1985 to 1987

Digital designer and integration coordinator for TOW2 Missile Autotrack program (Army). System incorporated state of the art VHSIC processors with an IR missile tracker. Primary responsibility was digital design of several boards. Also led 4 engineers in effort to get system from prototype to initial production.

APS116 Radar Test Equipment 1979 to 1984

Digital designer for Radar automatic test equipment systems. Installed mods on aircraft carriers.

EDUCATION:

1982-1986 M.S.E.E., Southern Methodist University, Dallas, TX

1976-1979 B.S.E.E., Virginia Tech, Blacksburg, VA

PATENTS: A total of 11 patents including:

Color Burst Queue for A Shared Memory Controller in a Color Sequential Display System

Method of Synchronizing Video Sources Using Slow PLL Approach

Temporal dithering to increase dynamic range of images in sequentially illuminated displays

NOTEWORTHY AWARDS:

1997 Emmy award for technical achievement as part of team that designed Grand Alliance High Definition digital video system.

2011 Outstanding research employee for delivering two major projects in unrelated fields in the same year.

PUBLICATIONS:

D. Stanton, J. Shimizu, and J. Dean. “Three Lamp Single Light Valve Projector," Society for Information Display Conference 96, San Diego, June, 1996.

P. Janssen, J. Shimizu, J. Dean, and R. Albu. “Design aspects of a scrolling color LCoS display," Elsevier Science Displays, volume 23, issue 3, June, 2002.

J. Dean, V. Gornstein, M. Burcher, L. Jankovic. “Real-time photoacoustic data acquisition with Philips iU22 ultrasound scanner,” Photons Plus Ultrasound: Imaging and Sensing 2008: The Ninth Conference on Biomedical Thermoacoustics, Optoacoustics, and Acousto-optics

HOBBIES: Competitive running, basketball, darts, road cycling

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