Ritu Garg
M.E., Computer Science and Engineering, PEC Chandigarh
91-977******* ********@*****.***
Objective:
To seek a place where I can dedicate myself as a software professional putting together affluent technical knowledge
Executive Summary:
5+ years of Experience in software development using C and C++
Sound knowledge of Algorithms and Data structures
Intensive programming in C
Hands on Experience on complete Software development Life Cycle
Excellent analytical and problem Solving skills
Analytical Thinker, Quick learner, Team player and Open to work with new technologies
Technical Skills:
Operating Systems
Unix, Windows Xp/Vista
Programming Languages
C, C++,visual basic
Configuration Management
Clear Case.
Editors
Cygwin, gvim, vi, Ultra Edit, Edit Plus
Bug Tracking
Mercury Quality Center, Test Man, DETS, Nokia Web Pronto
Other tools
Source Insight, GNU Debugger (GDB), Valgrind (Memory Leaks), Strace, RTRT (Code coverage, Memory profiling, Performance Profiling),Make (Executables generation controller), SRT, Tera term, HP Quality center and few Aricent and NSN proprietary tools, Beyond Compare
Key Skills
C,C++, Algorithms, UNIX, Data Structures
Professional Experience:
Worked in Aricent Holdings Ltd. as a Software Engineer
Aricent is a CMMI level 5 global innovation, technology and services company focused exclusively on communications. It is a strategic supplier to the world's leading application, infrastructure and service providers, with operations in 19 countries worldwide.
Worked in Samsung India Software operations as a Lead Engineer
SISO, Bangalore works in conjunction with Samsung, Korea to execute various software development and testing projects for Samsung/OEM Printers, Multi-Function Devices and Bundled Utilities.
Worked in Cadence Design Systems Ltd as a SMTS
Cadence is an electronic design automation (EDA) software and engineering services company, producing software for designing chips and printed circuit boards.
Project : RTL Compiler(Nov’11 – Dec’13)
Summary
OS : Linux
Product: RTL Compiler
Language : C++
Role : SMTS
Team Size: 4
Description
RTL is a tool to perform global RTL design synthesis to accelerate silicon realization With multi-objective optimization (timing, area, and power intent) and support for advanced low-power design techniques.
I am working on a module called Incremental Optimization which is a last step in RTL synthesis.
Objective of Incremental Optimization is to optimize the netlist on various parameters like worst negative slack, area and total negative slack.
Responsibilities
To execute the large customer designs to analyze the run time issues.
To fix the ccrs related to various features.
To run the weekly benchmarks to analyze the QoR impact of latest checkins
To work towards enhancement of various tricks in iopt to enhance QOR.
Tools Used
Clear Quest (CQ),CCMS,GDB,Tcl
Project: Printing Commercial Projects (Oct’ 2010 – Sep’ 2011)
Summary
OS : Linux
H/W : Printers (7 inch models)
Language : C
Role : Lead Engineer
Team Size: 10
Description
The project handles the B2B requirements and new feature implementation requests very frequently as required by customers for Rushmore, Rushmore M, Elbert and Rose R models of printers.
Responsibilities
Design the feature enhancement flows
To write code in C to implement new features while ensuring that existing functionality is not broken.
To identify all possible test scenarios and to write test cases.
Execution of Unit and sub system integration level testing.
To fix challenging bugs in various modules of the product.
Peer Code reviews
To handle the releases
To Participate in BS Reviews
Tools Used
Microsoft Visual Studio, Clearcase, Clear Quest (CQ)
Project: Medusa (Jul’ 2008 – Aug’ 2010)
Summary
OS : QNX
H/W : System Module
Language : C
Role : Software Designer and Developer
Team Size: 3
Description
Medusa is a 2G Flexi Multi BTS from Nokia Siemens Networks, which shall be later evolved to Support concurrent 2G/3G/LTE operation. Fault management module in System Operations and Management domain is implemented as a task in QNX written in C. It is responsible for receiving fault indications from various modules and domains and sending alarm messages to BSC and Element manager after reclassifying them to correct object. It is also responsible for canceling and reissuing the alarms after an object is locked/blocked and unlocked/unblocked respectively.
Responsibilities
Co authored functional flows of fault management.
Handled ownership of multiobject alarm feature.
To create High level and low level Designs for new features in Fault Management.
To write code in C to implement new features while ensuring that existing functionality is not broken.
To identify all possible test scenarios and to write test cases.
Execution of Unit and sub system integration level testing.
To fix challenging bugs in various modules of the product.
Tools Used
C, Shell scripting, Vi Editor, GDB, Clearcase, Mercury Quality Center, Test Man, DETS, Nokia Web Pronto, Rational test real time(RTRT)
Projects in College:
Project : Innovated and implemented a Protocol to deal with disassociation and deauthentication attacks in 802.11 wireless networks(Nov 2008 – May 2009)
Description:
Simulated an 802.11 wireless network and implemented a probabilistic solution to deal with disassociation and deauthentication attacks.
Technologies used:
C++, Network Simulator
Platform:
Linux
Project : Erased File Recovery System
Description:
This project is responsible for recovering erased files on FAT 32 system.
Technologies used:
C
Platform:
Windows
Project : Academic Information System
Description:
An automated system to maintain the processes like student information system, course management and result management which prevents data discrepancy and data redundancy.
The solution provides a easy to use interface so that all users can use it easily without a long training.
Technologies used:
Visual Basic
Platform:
Windows
Project : Two Pass Assembler
Description:
It does parsing of source code (input file) and generates machine code for 0x8086 architecture.
Technologies used:
C
Platform:
Windows
Academic Profile:
M.E. in Computer Sci. and Engg.
Punjab Engg. College
(PEC), Chandigarh
2006-2008
9.2(CGPA)
B.E. in Computer Sci. and Engg.
SLIET, Longowal(Punjab)
2003-2006
72%
Diploma in Comp. Sci. and Engg.
Thapar Polytechnic Patiala (Punjab)
1999-2002
65%
Matriculation
Punjab School Education Board
1998-1999
84.5%
Achievements & Rewards:
GATE qualified with 97 percentile.
1st prize for Genia-Mania competition organized in TECHFEST-2004 at SLIET, Longowal.
3rd prize for Microprocessor competition organized in TECHFEST-2004 at SLIET, Longowal.
Awarded certificate for being a part of NSS in TEECHFEST-2003 at SLIET, Longowal.
Awarded certificate for membership and contribution to MAGPI club at PEC, Chandigarh.
Personal Details
Date of Birth : 23rd May, 1985
Father’s Name : Surjeet Garg
Marital Status : Single
Interests : Music, Reading, Algorithms, Puzzle Solving
Languages Proficiency: English, Hindi
Declaration:
I hereby declare that all the information is complete and true to the best of my knowledge.