Engineer Design

M NITIN KUMAR

B.E in Electronics and Communication Engineering,

ASIC Design and Vrification Trainee at CVC Pvt Ltd.

Address: #***, **** ****, ****** *,

HSR Layout,

Bangalore – 560102

Mobile: +91-720*******

Email: *****.****@*****.***

*****@*********.***

Objectives

To secure a challenging career leveraging a strong background in electronics, where I can add value to the entity that enhances my ability, inherent skills and provide a fulfilling professional experience.

Skills

Hardware Description Language : Verilog, SystemVerilog

Hardware Verification Language : SystemVerilog

Verification Methodology : UVM

Programming Language : C, Embedded C

Platforms : UNIX, Windows

Tools Used : QuestaSim, Quartus, Cadence Virtuso

Technical Expertise

ASIC, FPGA, Digital Design, Microprocessors and Microcontrollers, System on Chip (SoC), RTL Coding, FSM based design, Functional Simulation, Synthesis, Code Coverage, Functional Coverage, DRC, LVS, Digital Layout Design, Circuit Simulation, LT Spice, Hardware Testing, Comprehensive Fuctional Verification

Professional Experiance

ASIC Design Verification Engineer Intern, Verifxn Pvt Ltd, 2014

ASIC Design Verification Engineer Trainee, CVC Pvt Ltd, 2015

Academic Profile

Degree

Board/University

Year

Percentage

B.E

[ECE]

Visveswaraya Technological University

2014

60.00

P U C

[PCME]

Karnataka

2010

75.30

S S L C

CBSE

2008

68.62

Certificate Of Participation

Certified on “Programming Using C” from IIHT

Certified on “ASIC Design Verification Trainee” from CVC Pvt Ltd

Achievements

Published a conference paper titled “Coverage Closure – is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure?”, at DVCON India, Conference and Exhibition, 2015.

Technical Conference on paper Titled “Network On Chip”, National Conference on Computing, Communication and Networking, 2014.

Projects

1) Verification of AHB to SPI Interface Protocol

Constructing an UVM based testbench for AHB to SPI interface protocol. The design is simulated using QUESTASIM.

Team Size: 3

Status: On-going

2) Design and Verification of AMBA APB 3.0 based Extencible Memory controller

Designed AMBA APB 3.0 based Extencible Memory Controller using Verilog, constructed System Verilog based testbench to verifiy the design, generated the code and functional coverage report. The design is simulated in QUESTASIM

Duration: 3 months

Team Size: 3

Status: Completed

3) Automated Anti-Lock Braking System(ABS) Based On Road Surface

Constructed the mechanical design structure to support the ABS System, formulated the working algorithm of the system.

Duration: 6 months

Team Size: 4

Status: Completed

Personal Strengths

Good at team work

Rapid at learning things

Honest and hardworking

Willingness to learn

Good communication skills, optimistic and positive attitude

Personal Profile

Name

M. Nitin Kumar

Father’s Name

A. Muthu Selvan

Date of Birth

13/09/1992

Languages Known

English, Hindi, Tamil, Kannada, Tulu

Gender

Male

Maritial Status

Single

Nationality

Indian

Declaration: I hereby declare that the above-mentioned information is correct up to my knowledgr and I bear the responsibility for the correctness of the above-mentioned particulars.

Place: Bengaluru

Date: (M.Nitin Kumar)

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