Project Design Engineer
Resume:
Ravindra Prasad Reddy B V
E-mail: *******************.***@*****.***
Mobile: +91-917******* www.siliconsys.in
Institute of Silicon Systems Pvt. Ltd.
CAREER OBJECTIVE:
To get an entry level Physical Design engineer position in VLSI industry, which enables me to update with the emerging latest Technology and provides scope for widening the spectrum of my knowledge.
ACADEMIC QUALIFICATIONS:
M.Tech in VLSI System Design from Vignan Institute of Technology & Science (VITS) affiliated to JNTU-HYDERABAD with an aggregate of 74.06% in 2015. B.Tech in Electronics and Communication Engineering from Kasireddy Narayan Reddy College of Engineering and Research (KNRCER) affiliated to JNTU-HYDERABAD with an aggregate of 73.78% in 2012.
Intermediate (MPC) from Nalanda Junior College affiliated to Board of Intermediate Education –Andhra Pradesh with an aggregate of 81.30% in 2008. 10th from Balaji High School affiliated to Board of Secondary Education –Andhra Pradesh with an aggregate of 84.50% in 2004 .
INDUSTRIAL TRAINING:
Trained in VLSI-Physical Design from Institute of Silicon Systems Pvt. Ltd... Hyderabad from August 2015 to December 2015 using Cadence tools. Cadence Tools:
SoC Encounter - for Floor-Planning, Power-Planning, Place and route
ETS - for Sign-off timing closure
RTL Compiler - for Logic Synthesis
Virtuoso Layout Editor - for standard cell Layout
Assura - for DRC and LVS checks
PROJECTS:
Physical Design:
PROJECT 1 : BLOCK 4
Gate Count : 296296
Cell Count/Macros : 74074/12
No of Clocks : 17
Frequency : 200MHz
Metal Layers : 6
Technology Node : 90nm
Role : To perform Audit Checks, Floor-plan, Power-plan, Placement, Trail- Route, Congestion Analysis, CTS, Detailed Routing, Timing closure Ravindra Prasad Reddy B V
E-mail: *******************.***@*****.***
Mobile: +91-917******* www.siliconsys.in
Institute of Silicon Systems Pvt. Ltd.
PROJECT 2 : BLOCK 3
Gate Count : 1074460
Cell Count/Macros : 37654/2
No of Clocks : 6
Frequency : 227MHz
Metal Layer : 6
Technology Node : 45nm
Role : To perform Audit Checks, Floor-plan, Power-plan, Placement, Trail- Route, Congestion Analysis, CTS, Detailed Routing, Timing closure PROJECT 3 : BLOCK 2 (Top Level)
Gate Count : 128929
Cell Count/Macros : 24462/12
No of Clocks : 4
Frequency : 1499MHz
Metal Layers : 5
Technology Node : 130nm
Role : To perform Audit Checks, Floor-plan, Power-plan, Placement, Trail- Route, Congestion Analysis, CTS, Detailed Routing, Timing closure PROJECT 4 : BLOCK 1
Gate Count : 7701
Cell Count/Macros : 2477/0
No of Clocks : 3
Frequency : 333.3MHz
Metal Layers : 5
Technology Node : 180nm
Role : To perform Audit Checks, Floor-plan, Power-plan, Placement, Trail- Route, Congestion Analysis, CTS, Detailed Routing, Timing closure Logic Synthesis:
Project 1 : Design -1
Objectives : To run Zero Wire Load, Auto Wire load and Force Wire Load synthesis
Tools : RC Compiler
Gate count / Area : 280 / 363µm
No. of Clocks : 2
Frequency : 200 MHz
Technology : GF 65nm (Global Foundries)
Role : Writing SDC, TCL Scripts, Extracting timings, Optimizing ATP
Ravindra Prasad Reddy B V
E-mail: *******************.***@*****.***
Mobile: +91-917******* www.siliconsys.in
Institute of Silicon Systems Pvt. Ltd.
Project 2 : Design - 2
Objectives : To run ZWLM Synthesis and to achieve maximum possible Frequency with different VT’s
Tools : RC Compiler
Gate count / Area : 5816/6261µm (RVT) 4388/4018µm (HVT) 4508/4086µm
(MVT)
No. of Clocks : 1
Frequency : 500 MHz
Technology : GF 65nm (Global foundries)
Role : Writing SDC, TCL Scripts, Meeting ATP’s with zero slacks LAYOUT:
Objective : Designing of Standard Cells
Cells : AND, OR, NAND, NOR, INVERTER, 5*5 Matrix
Tools : Virtuoso Layout XL Editor, Assura Verification for DRC and LVS Technology : TSMC130nm
Role : Developing the Layout from spice net-list & verifying DRC, LVS Challenges : Routing using single metal layer by following metal’s pitch and Half- DRC Rules
ACADEMIC PROJECTS:
Title: Design of multiplexer based Low Power 6-bit FLASH ADC Description:
6-bit Flash Analog to Digital Converter [ADC] in 130-nm technology CMOS logic functions at 2.5-GSamples/s, used in most of DSP-based receiver. A multiplexer logic is compared with the encoder using Full Adders in Wallace tree structure, with respect to hardware, power consumption. The Multiplexer logic is used to convert the 63-Bit Thermometer code into 6-Bit Binary code. The ADC with 400mV of full scale voltage consumes 15-30 m W of power approximately from a 0.9V supply. PERSONAL PROFILE:
Father’s Name : B. V. Pedda Ramana Reddy
Mother’s Name : B. Bhagya Lakshmi
Date of Birth : 06-06-1989
Languages Known : Telugu, English, and Hindi
Current Location : Hyderabad (Flexible to migrate)
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