Analog Layout Engineer
Resume:
Career Objective:
Looking for a responsible position as Analog Layout Engineer in a reputed organization where performance is rewarded with new responsibilities and opportunities.
Technical Skill:
Floor Planning, Placement and Power Routing.
DRC and LVS.
Knowledge of analog layout design techniques like matching, shielding and guard ring.
Knowledge of take cares various layout effects like antenna effect, EM, Latch-up, IR drop and Crosstalk.
Good understanding of layout dependent effect at lower technology.
Knowledge of FDSOI Technology.
Knowledge of FinFET Technology.
Basic Knowledge of ESD circuit and ESD cell layout design.
Knowledge of MOSFET Device Physics and Semiconductor Memories.
Knowledge of CMOS and BiCMOS fabrication.
Knowledge of Basic Analog CMOS circuit.
Knowledge of SOI and Bulk Substrate.
Work Experience:
Organization: Institute of Silicon System Pvt Ltd., Hyderabad.
Role: Custom Layout Design Trainee.
Work: Work on Standard Cells Layout, Analog Layout and Memory Layout Projects.
Tools: Cadence tools used for work on projects.
Cadence Virtuoso: Layout Editor (L and XL).
PVS: DRC and LVS verification.
Assura: DRC and LVS verification.
Targeted Technologies: GPDK 45nm and TSMC 130nm.
Duration: May 2015 to December 2015.
Custom Layout Projects
Digital Layout Design Project
1.Standard Cells Layout Design
Standard Cells: INV, NAND, NOR, AND, OR, XOR, XNOR, MUX and DFF.
Targeted Technology: TSMC 130nm.
Role: Drawing stick diagrams from spice netlist, developing the layout and verifying DRC & LVS.
Challenges: Drawing the Layout in optimized way using only Metal1, maintaining cell height in terms of Metal2 pitches and following half DRC rules for each cell.
Analog Layout Design Projects
Targeted Technology: GPDK 45nm.
Role: Develop layout from schematic, make floor planning, power planning and get DRC & LVS clean.
2.Level Shifter (LS)
Challenges: Taken care of PSUB2 and drawing the layout in optimized way.
3.Operational Amplifier (OpAmp)
Challenges: Minimum poly routing, matching the current mirrors and Diff. pair.
4.Band Gap Reference (BGR)
Challenges: Applying matching techniques for BJT's and resistors. Providing guardring and drawing the layout in optimized way.
5.Digital to Analog Converter (DAC)
Challenges: Matching resistors, take equal routing for switches, matching the mismatches to meet the same delay. Placement of Dummies around resistor. Taking more care on latch-up issues, antenna Effect, and EM.
6.Phase Lock Loop (PLL)
Challenges: Matching the mismatches to meet the same delay, placement of Dummies. Taking care on latch-up issues, antenna effect, EM and shielding for critical nets.
7.PG Comparator (PGCOMP)
Challenges: Matching the current mirrors and Diff. pair. Placement of Dummies. Taken care of PSUB2, EM and drawing the layout in optimized way.
8.Analog Reference OTA
Challenges: Applying matching techniques for BJT's, mosfet and resistor. Placement of capacitor, transistor, and resistor. Providing guardring and drawing the layout in optimized way.
Memory Layout Design Project
9.SRAM_MAC5 (32 BIT)
Role: Worked on 6T SRAM cell, 5bit i/n to 32bit o/p decoder, latch, sense amplifier and SRAM_MAC_5 cell with verification (DRC/LVS) clean.
Challenges: Followed fixed 12 metal tracks cell height and made plan for easy routing for READ and WORD Buses.
Personal Skill:
Adaptable to work as part of team.
I enjoy acquiring new skills.
Can work for prolonged hours to meet deadline of projects.
Educational Qualification:
Completed B.Tech in Electronics & Communication Engineering (ECE) from Rajasthan Technical University, Kota with an aggregate of 68% in 2015.
HSC from Smt. S. K. Pathak Vidhya Mandir (Gujarat Secondary and Higher Secondary Education Board) with an aggregate of 48.42% in 2009.
SSC from Shree J. A. Sanghvi High School (Gujarat Board of Secondary Education) with an aggregate of 62.16% in 2007.
Personal Profile:
Father’s Name : Ramesh Bhai Hanani.
Nationality : Indian.
Language Known : English, Hindi and Gujarati.
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