Design Electrical Engineering

Elisiel Medina

**** **** ***. ******, ** *****• 630-***-**** • *********@*****.***

EDUCATION

University of Illinois Chicago, IL Bachelors of Science in Electrical Engineering Graduated December 2015

SKILLS SUMMARY

Over two years of digital logic design experience in both CMOS and VLSI technologies

Proficient in computer architecture layout and testing using Cadence Virtuoso and Quartus II Simulator

Fundamental understanding of CMOS and VLSI technologies that includes gate-level design, substrate layout and performance analysis

Synthesized chip designs using Synopsys Design Compiler and performed static timing analysis (with parasitic extraction)

Thorough understanding of chip architecture (CPUs, buses, I/Os, clocks, resets, etc.)

Working knowledge of VHDL, Verilog, C++, MIPS assembly language

Good understanding of buck, boost converters for design in switch-mode power supplies

Excellent communication and teamwork skills

Fluent in Spanish, both written and spoken

WORK EXPERIENCE

Arthur Harris & Co. Chicago, IL

Quality Control, Welder June 2005 – August 2013

•Weld various gage stainless steel floats using a Thermal Arc welding system

•Produce a smoothly finished seam on each float to ensure strength and ductility as these would be used in high pressure environments such as boiler feed systems and steam traps

•Individually tested each float under a pressurized system to ensure a 100% safety factor (for example, a float used at 100 lbs. pressure should have a minimum 200 lb. collapse pressure)

•Fabricate stainless steel tubes on a manual lathe, making sure tolerances were within customer’s requirements

Heitman Architects Itasca, IL

Architectural Intern March 2009 – May 2009

•Produce AutoCAD 2D designs of window structures for a bank (dimensions of rails, window panes, etc.)

•Render building layout of a warehouse using Revit

•Create hand renderings of building facades in relation to their material (brick, aluminum, concrete, etc.)

SENIOR DESIGN PROJECT

Low-power, high frequency 4-bit synchronous ALU using 250nm SOI technology

Layout Designer September 2015 – November 2015

• Constructed and simulated functional logic blocks using Cadence Virtuoso to perform a specified set of instructions

• Among the operations used were 4-bit Addition, 2’s complement, 4-bit Add-traction, 4-bit NAND, 4-bit NOR, 6-3 MUX for output selection, D-flip flop for static memory storage

• Optimized layout design for easy circuit implementation

• Completed DRC & LVS checks to add parasitic capacitances for timing analysis

• Added overflow and carryout detection for future implementation

DC/DC Boost Converter Design and Control

Power Electronics Designer September 2015 – December 2015

• Designed a CCM boost converter with the following specifications: Input voltage: 75V, Input Power: 750W, Output Voltage: 150V, Inductor current ripple: 15%, Capacitor Voltage ripple: 5%

• Determined nominal ESR values for capacitor and inductor

• Constructed bode plot of the open-loop boost converter to compare phase margins for different capacitor ESR values

• Ensured open-loop stability of the system

• Designed a current mode control to obtain a phase margin greater than 30 degrees

INTERESTS

•Long distance running and biking; daily runs of 4-6 miles

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