ANIL KUMAR H.A

acry7r@r.postjobfree.com

Mobile: +91-903*******

OBJECTIVE

To develop proficiency in the Semiconductor domain and to work in a globally competitive environment that shall yield the twin benefits of the job satisfaction and a steady paced professional growth.

EDUCATION

M.Tech in VLSI design (2013 – 2015) from VIT University

CGPA: 7.56

B.E in Electronics and Communication (2007 - 2011) from Sapthagiri College of Engineering, Affiliated to VTU, Belgaum, Karnataka.

Percentage Score: 70.8%

Intermediate (2005 – 2007) from S.Nijalingappa Pre-university College Bangalore, State Board, Karnataka.

Percentage Score: 78.16%

Secondary School Examination (2005) from St’annes High School Hesaraghatta, Bangalore, State Board, Karnataka.

Percentage Score: 88.80%

TECHNICAL SKILLS

Languages C language, Core JAVA, SQL, Perl Scripting, Verilog HDL, TCL

Tools Xilinx: ISE, Chipscope, XPE

Cadence: Virtuoso, Encounter, LVS

LASI

Skills ASIC Design, Digital Design, Low Power design, RTL

SUMMARY OF PROJECTS

Implementation of Fast Radix-10 BCD multiplier on FPGA: In this project a BCD multiplier is designed for fast multiplication. The methodology has three steps Partial product generation, Reduction and Converting back to BCD. Multiplier is designed to multiply two 16 digit (64-bit) numbers. Properties of BCD number like redundancy,

excess-3 and overloaded decimal digit encoding are used to reduce the complexity of

the multiplier to achieve lesser area on silicon. The design is implemented in Virtex-5 FPGA using Xilinx ISE 14.1 and Verilog HDL. Xilinx XPE is used for power analysis, Chipscope pro analyzer for debugging and verifying the results.

Implementing Digital FIR filter using Fast FIR Algorithm on FPGA: Fast FIR Algorithm is one of the algorithm technique used to perform the FIR filter operation at relatively faster rates than that of conventional filter. The digital FIR filter was designed using Fast FIR algorithm along with the property of symmetric coefficients. The designed filter resulted in reduced silicon area, power consumption with an enhanced speed. The filter designed using Verilog hardware descriptive language and implemented on Altera FPGA board.

Virtual touch interface (B.E project): This work is to develop a human machine interface using advanced Image Processing technique for controlling devices (Robot) in Real time environment.

Tools used: MATLAB v7.5, MPLAB 7.4, Embedded C.

Platform: WINDOWS XP

Communication: RF communication with ASK modulation.

Code written using - Embedded C, MATLAB

COURSES TAKEN

FPGA based system design

ASIC Design

Digital IC design

Analog IC design

VLSI Testing and Testability

Scripting Language – Perl, TCL

IC technology

Low power IC design

VLSI digital signal processing

CAD for VLSI

SOC design

ACHIVEMENTS

Publications: Published paper on “Implementation of Fast Radix-10 BCD Multiplier in FPGA”, in Indian Journal of Science and Technology, Vol 8(19), IPL0147, Aug 2015.

Presented a poster titled “Implementation of Fast Radix-10 BCD Multiplier in FPGA” at the Emerging Trends in Engineering and Technology symposium.

EXTRA CURRICULAR ACTIVITIES

Attended and conducted Robotic workshops.

Volunteered in blood donation camps, cultural and social activities.

Participated in poster presentation conducted by VIT University during “Standards Week”.

SOFT SILLS

Good Communication Skills.

Ability to work individually and in group.

Good Analytical skills, Quick to grasp new technologies.

HOBBIES

Listening music

Playing Cricket

Magazine

Trekking.

PERSONAL DETAILS

Date of Birth : 24th June 1989.

Nationality : Indian

Languages Known : English. Hindi, Kannada, Telugu

Permanent address : #949, opp to GMP school, Hesaraghatta, Bangalore,

Karnataka, India.

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