CURRICULUM VITAE
SOURABH VIJAYVARGIYA * ****.******@*****.***
Objective
To make contribution to the organization to the best of my ability and to develop new skills and share my knowledge while interacting with others and achieve new height and gives exposure and implementation of emerging new technologies.
Professional Summary
Overall 1+ Year of experience in Embedded System Development at AvioHeliTronics Infosystem Pvt. Ltd.
Development of Embedded system using C programming language.
Hands on Experience on Serial Communication Protocol like UART Protocol.
Knowledge of CAN Protocol and SPI Protocol.
Ability to meet Tight Deadlines and works under pressure.
Adaptability and Fast Learner.
Education
Class/Course
Name of Institute
Board/University
Year of Passing
Marks%
B.Tech(HONOURS)
(E&C)
JEC College, Jaipur
R.T.U. Kota
2014
72.2%
Intermediate
Maa Bharti Vidhya Bhawan, Kota
R.B.S.E.
2009
80%
S. S. C
Sanskar Bharti Secondary School, Bijoliya;
R.B.S.E.
2007
77%
Technical Skills
Programming Languages
C, MATLAB, Embedded
Operating Systems
Windows, Linux
Tools
QT, MATLAB, MS-Office, Xilinx, Model-sim, Multisim, QuartusII, AutoCAD.
FPGA Boards
Altera Cyclone V, Cyclone III Development Board.
Area of field interest _
C, Embedded C, Embedded system, Data Structures
Work Experience
Overall Experience : 12+ months.
Training Experience : 1 month in Airport Authority of India (AAI) of Communication, Navigation & Surveillance. (Trainee of Communication, Navigation and Security equipment’s like DVOR, DME, X-ray baggage, Glide path, Localizer, CCTV etc.).
Project Title: #1 VGA Video Generation
Designation : Design Engineer
Duration : Jan 2015- March 2015
Description: Completed IP core for Video generation of VGA technique on FPGA for Avionics application. In this we have transmitted the image through MATLAB, receive on FPGA and sent to Screen via VGA cable.
Project Title: #2 DES: Data Encryption Standard algorithm implementation
Designation : Design Engineer
Duration : March 2015- May 2015
Description: DES is a data encryption technique which is based upon Algorithm and certain Randomized technique. All the step of algorithm is successfully implemented in QT.
Project Title: #3 Error Detection Techniques
Designation : Design Engineer
Duration : Sep 2014- Dec 2014
Description: Completed IP Core of Encoding and Decoding Techniques including Convolution Encoding, CRC, and Viterbi Decoding.
Personal profile
Name : Sourabh Vijayvargiya
Date of birth : 27-09-1992
Sex : Male
Languages known : English, Hindi.
Nationality : Indian
Address : 935, Mandakini marg, Near Panchayat Chowk
Bijoliya, Dist.- Bhilwara (Rajasthan) -311602
Hobbies : Listening music, Bike riding, Interest in new technologies
Declaration
I do hereby declare that the information stated above is true to the best of my knowledge.
Place: Bangalore
Sourabh Vijayvargiya