Design Engineer

Kodeeswaran S

Mobile: +91-897*******

Email: *******************@*****.***

CARRIER OBJECTIVE

To be an enthusiastic and energetic engineer eager to take up challenging jobs that provides opportunity for my growth and to gain experience.

ACADEMIC QUALIFICATION

Master of Engineering (ME), Applied Electronics from Regional Centre Of Anna University, Coimbatore in 2015 with 7.5 CGPA.

Bachelor of Engineering (BE), Electronics and Communication Engineering from Sona College of Technology, Salem (Anna University Chennai) in 2008 with an aggregate 71%.

HSC – Sengunthar Mahajana Higher Secondary School (State Board) – Tharamangalam, Salem in 2004 with 89.25%.

SSLC – Sengunthar Mahajana Higher Secondary School (State Board)–Tharamangalam, Salem in 2002 with 79.40%.

PROFESSIONAL EXPERIENCE

Worked as a part time trainer in Arrow Creative Academy, Coimbatore from Feb’2014 to Jun’2015.

Roles and Responsibilities:

Training the students in both VLSI and Embedded system (PIC Controller).

Worked as a VLSI Design Engineer (R&D) in E-SoftLabz, Bangalore from 2011 to Aug 2013.

Roles and Responsibilities:

To carryout detailed study of design given by the client and making basic block diagram/design flow.

Preparing individual logic diagram for each block and discussed with client.

Finalization of block and making flow chart for that.

The finalized block can be developed using verilog code.

The design can be verified by simulation Tool.

Finally obtaining the design parameters are satisfy client as per their requirement.

Worked as a Lecturer in Kottai Marriyamman Polytechnic College, Salem from June 2009 to May 2011.

Roles and Responsibilities:

Handled embedded system, VLSI and Real Time Applications subjects.

Acted as class Teacher and Project Co-coordinator.

SKILL SET

HDL’s : Verilog HDL, and VHDL

EDA Tools : Modelsim, Xilinx13.1ISE, Questa Sim, QuartusII (Altera), Microwind.

H/W Expertise : Xilinx FPGA Trainer Kit Spatan3AN

Programming Languages : C, C ++ (Intermediate)

Domain : ASIC/FPGA Design Flow, Digital Design Methodologies

Knowledge : RTL Coding, FSM Based Design, Simulation, and Synthesis

Bus Protocols : Basics of UART(RS232).

PROJECTS

Project Name : FPGA implementation of Cryptographic processor based on

Public key algorithm.

Tools Used : Xilinx 10.1 ISE, ModelSim 6.4 SE.

HDL : Verilog HDL.

Description

This work explains design a processor which has both general purpose instruction and security instructions. It have been developed using public key and secretes key algorithms in Verilog HDL algorithms in Verilog HDL and the design could be verified and obtained RTL schematic can be generated using synthesis Tool.

Project Name : Reliable Routing & Deadlock free massive NoC Design with Fault

Tolerance using de Brujin graph.

Tools Used : Xilinx 10.1ISE, ModelSim 6.4 SE.

HDL : Verilog HDL.

Description

It deals with generalized binary de Bruijn (GBDB) design as a reliable and efficient network topology for a large NOC unit. This design could use deadlock free and reliable routing algorithm to detour a faulty channel between two adjacent switches. The RTL implementation of the proposed reliable routing has been shows optimal improvements in parameters.

ACADAMIC PROJECTS

PG PROJECT

Project Name : FPGA Implementation of High Speed Unified Field Crypto-processor

For Security Applications

Tools Used : Xilinx 10.1ISE, ModelSim 6.4 SE

HDL : Verilog HDL

Description

This project talks about design unified field processor design with security instruction. Unified field means “Keeping prime and binary extension arithmetic model” and invoking pipeline concept to make processor to achieve high speed.

CO-CURRICULAR ACTIVITIES

Done on PG Diploma in Embedded Solution in the year Aug 2008 to Feb 2009 at Anna University, Trichy.

Personal Details

Father’s Name : A.Sivaprakasam.

Sex : Male

DOB : 06.06.1987

Nationality : Indian

Marital Status : Single

Languages Known : Tamil &English, Kannada (understand)

Permanent Address : New 12th ward, Kizhakathi KuppannaMudali Street,Tharamangalam.

Salem-636502.

DECLARATION

I hereby declare that the above information is true to the best of my knowledge and belief.

Date:

Place: (KODEESWARAN)

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