Verilog, System Verilog, Shell Scripting

SHRUTI MURGAI

Permanent Address: Metro Enterprises, New Arya Smaaj Complex, Roura-II, Bilaspur (H.P.).

Email id: ************@*****.***,

******.******@*****.***

Contact: +91-880*******, +91-889*******

OBJECTIVE

Seeking a challenging job within an organization where I can contribute to its success through my designing and verification skills and synchronize with new technology while being resourceful, innovative and flexible.

EDUCATION

Course

Branch

Institution

University/ Board

Year of

Passing

%

Marks

M-Tech

VLSI Design

Amity School of Engineering & Technology

Amity University

2015

89.7

B-Tech

Electronics & Communication Engineering

Beant College of Engineering and Technology

Punjab Technical University

2013

75.63

SSC

Science Group

H.A.P.S. Hamirpur

HPBSE

2009

86.6

HSC

D.A.V. Bilaspur

CBSE

2007

78.6

AREA OF INTEREST

ASIC/ FPGA Design flow,

Digital Circuit Design

RTL coding & Verification

TECHNICAL SKILLS

HDL/HVL Verilog, System Verilog, VHDL

SOFTWARE SKILLS Shell scripting (beginner), PYTHON (beginner), C#, C++

PLATFORMS Windows, Linux/Unix

SOFTWARE TOOLS Xilinx, Questa Sim, HDL Designer Tool, Pyxis (Mentor Graphics), Labview, Comsole, Cadence (Schematic Editor – Composer, Layout Editor: Virtuoso), Silvaco (ATLAS and ATHENA), Visual Studio.

CERTIFICATIONS

Certification in System Verilog.

Certification in Verilog HDL and FPGA

Certificate in information technology(C#.NET & DBMS (SQL))

Certification in object oriented programming language using C++.

PAPERS PUBLISHED

Paper titled Energy Efficient And High Performance 64-Bit Arithmetic Logic Unit Using 28nm Technology presented at ICACCI-2015 held on 10-13 Aug 2015 at Kochi. Paper will be published under IEEE conference proceedings.

Paper titled Design and implementation of low power clock gated 64-bit ALU on ultra-scale FPGA accepted at ICCS-2015 to be held on 18-20 Oct 2015 at Pilani. Paper will be published under AIP Conference proceeding.

Paper titled Power efficient, clock gated multiplexer based full adder cell using 28 nm technology accepted at ICCS-2015 to be held on 18-20 Oct 2015 at Pilani. Paper will be published under AIP Conference proceeding.

Paper titled Design and implementation of power efficient 10-bit dual port RAM on 28 nm technology accepted at ICCS-2015 to be held on 18-20 Oct 2015 at Pilani. Paper will be published under AIP Conference proceeding.

Presented paper on topic VHDL SYNTHESIS LIMITATIONS AT NATIONAL CONFRENCE IAEISDISE-2014 at Solan on SEPTEMBER 12-13, 2014.

PROJECTS

M.Tech Dissertation:

Project Title: Energy Efficient and High Performance VLSI Circuits Using 28nm Technology.

Language: Verilog Tool: Xilinx Power Analyzer Tool, QuestaSim

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology.

Designed a multiplexer based clock gated full adder cell. Use of multiplexer reduced internal toggling, hence, dynamic power optimized. Negative latch based clock gating technique optimized clock power of the design. The reduction of 7.41% in total power of the circuit achieved without degrading the performance.

Energy efficient and high performance 64-bit Arithmetic and Logic Unit using 28 nm technology

Designed a 64-bit Arithmetic logic Unit. Optimized basic block of carry select adder by using a new full adder configuration. Total device power and hierarchy power optimized to 12.5 % and 53.39 % respectively and time to 3.07%.

Design and implementation of low power clock gated 64-bit ALU on ultra-scale FPGA

Designed a 64-bit power efficient Arithmetic logic Unit based on negative latch based clock gating technique. Total supply power optimized to 25.47%, 29.05% and 46.13% at 20 MHz, 200 MHz and 2 GHz frequency respectively.

Design and implementation of power efficient 10-bit dual port RAM on 28 nm technology.

Optimized the power of device by modulating clock power of the circuit. Total supply power optimized to 16.96%, 60.88%, 71.06% and 72.44% at 1 GHz, 10 GHz, and 100 GHz and 1 THz frequency respectively. (Team Size: 1)

M.Tech Minor Projects:

Project Title: Designing of 10-bit dual port SRAM

Language: Verilog Tool: Modelsim, Xilinx

Designed 10-bit SRAM having two ports. Removed the deadlocks. Verified some modules on System Verilog. (Team Size: 2)

Project Title: Bio Medical images image processing using FPGA

Language: Verilog Tool: XSG Simulink

To detect the tumour in MRI image. HDL coding was done into black box and integrated with the XSG Simulink.

(Team Size: 2)

Project Title: Detailed study on ETHERNET and designed some of the modules.

Language: Verilog Tool: Xilinx, Modelsim

Studied Ethernet modules and successfully simulated some of modules like FIFO, encoder, decoder, shift registers on Modelsim. (Team Size: 1)

Project Title: Detailed study on VHDL synthesis limitations and coding styles for the future.

Language: VHDL Tool: Xilinx

Detailed study on how simulation differentiates from synthesis. End to the verbosity in VHDL with the advent of VHDL-2008. (Team Size: 1)

B.Tech Major Projects:

Project Title: ABOUT.ME

Enable user to quickly build a personal and dynamic splash page that points visitors to your content from around the web. The website was able to link with various other social networking sites including Facebook, LinkedIn, Flickr, and Twitter.

(Team Size: 4)

Project Title: Design, Fabrication & Testing Of Microcontroller Based System That Transmits Information Through Wireless Channel.

8051 microcontroller based wireless communication system. Encoder HT12E, Decoder HT12D, Octal bus transceiver 74LS245, 8-bit Microcontroller with 4K Bytes Flash AT89C51. Signal from switches at transmitter side were used to operate LEDs at receiver side. (Team Size: 3)

B.Tech Minor Projects:

Six weeks summer training in study of networks in NOKIA AND SIEMENS COOPERATION, Noida. (Team Size: 6)

Six weeks college training in PCB Designing and transformer designing. (Team Size: 6)

WORKSHOPS ATTENDED

Worked as a volunteer on 17TH INTERNATIONAL WORKSHOP ON PHYSICS of SEMICONDUCTOR DEVICES from 10-13 DEC 2013 at AMITY UNIVERSITY, Noida.

Worked as a volunteer on INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS FROM 20-21 FEB 2014 at AMITY UNIVERSITY, Noida.

NATIONAL CONFERENCE IAEISDISE-2014, HELD AT MANAV BHARTI UNIVERSITY, SOLAN. 12-13 SEP 2014

IEEE SSCS Delhi Chapter 'DISTINGUISHED LECTURE COLLOQUIA' on 19 DEC 2014 AT ST MICROELECTRONICS, GREATER NOIDA.

AWARDS AND ACHIEVEMENTS

Awarded BEST SPEAKER AT NATIONAL CONFRENCE IAEISDISE-2014 at Solan for presenting paper on topic VHDL SYNTHESIS LIMITATIONS.

Secured Merit Rank in NIIT (Top 2%)

Merit List Holder And Secured 35th Position In Entire State in 10+2.

Awarded Scholarship Of Rs10, 000 By H.P.S.E Board After +1.

Secured ‘A’ Rank In AITSE.

CO-CURRILAR ACTIVITIES

Executive of college societies (ISTE, MAD).

Coordinated Various Events during Cultural and Technical Festival., Main organizer of AGAZZ 2010 at BCET.

School house captain during 10th in D.A.V. Bilaspur.

EXTRA-CURRILAR ACTIVITIES

1st Prize In Group Dance In Cultural Fest 2012, 3rd In TEQFEST In 2009

Won Miss Fresher Pageant in BCET Gurdaspur.

Won Rangoli Competition In TEQFEST In 2009,2010.2011

LANGUAGES KNOWN

English

French(Beginner)

Hindi

Sanskrit

Punjabi (Native Fluency)

DECLARATION

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars

Place: Delhi Shruti Murgai

References are available upon request.

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