Engineer Design

ANKITA SAXENA

Raleigh, NC, USA, *****

Phone: 919-***-**** acrs4x@r.postjobfree.com

SUMMARY

Design Verification Engineer with experience in System Verilog/ UVM methodologies, random and directed testing, debugging and coverage, currently involved in the verification of Qualcomm’s latest microprocessors.

I graduated with a Masters Degree in Electrical & Computer Engineering from North Carolina State University with coursework in ASIC design and verification, computer architecture, digital signal processing, communications. I aspire to get opportunities to work with a variety of chip designs and newer verification technologies, and expand my understanding and knowledge around the latest developments in ASIC.

WORK EXPERIENCE

Qualcomm (Raleigh, USA) CPU Design Verification Engineer (Contract)

(April 2015-Present)

• Write directed tests to verify functionality of ARM microprocessor and the memory system, using Perl scripts.

Netronome Systems (Massachusetts, USA) Design Verification Engineer

(Oct 2012-March 2015)

JOB PROFILE & RESPONSIBILITIES

Responsible for the verification of several blocks in the Memory Unit, such as Load Balancer, Misc Engine

Developed a new suite of random test cases using System Verilog, ran tests against RTL simulations

Modified the monitor/transaction object classes for testing of new and previously untested design features

Added infrastructure to the test bench for new verification features, e.g. backdoor register reads for UVM registers

SIGNIFICANT ACHIEVEMENTS

Brought code and functional coverage to closure levels by tweaking constraint weighing, writing directed tests to hit missing points

Triaged and debugged random and directed test fails, found many RTL functional bugs in the blocks for which I was responsible

On inheriting the testing of some previously tested blocks, found some already existing bugs which were previously missed by debugging previously ignored regression failures

Qualcomm (Raleigh, USA) CPU Verification Engineer(Contract) (July 2012 – Oct 2012)

• Debugged and triaged test fails for random and directed test cases for verifying the functionality of an ARM micro-processor

Aricent Technologies (Gurgaon, India) Software Engineer (Nov 2008-July2010)

Developed a tool in Java to convert Rel99 CDMA call data from customer logs to product usable format

Designed and implemented the Java based GUI for a number of features of performance tester product

TECHNICAL SKILLS

Domain:DSP, Communications, ASIC Design /Verification, RF Design, Microprocessors, Error Correction Coding, Data Compression

•Digital Packages:C, Java, Unix, MATLAB,Orcad, Verilog, System Verilog, UVM, Perl, Shell scripting

PROJECTS & PRACTICAL TRAINING

North Carolina State University

ASIC Design Project (Jan 2011 – Apr 2011)

•Designed a Viterbi Decoder in RTL to compute most probable states from a given hidden Markov model using Verilog HDL, verified correct functionality using ModelSimlogic simulation software

•Designed circuit was optimized for area and delay and synthesized to gate-level description using Synopsys Design Vision

ASIC Verification Project (Aug 2011-Dec 2011)

•Created an object-oriented layered testbench using System Verilog to verify the functionality of all stages of a LC-3 microprocessor

• Constrained random tests were generated and functional coverage convergence was checked using QuestaSim

Cache and Memory Hierarchy Design (Jan 2012-Feb 2012)

•Designed a generic Cache class using Java and used it to implement memory design with two cache levels

• Explored the effects of varying no. of caches,cache size, block size, associativity of the caches and found some optimum combinations in terms of performance, area& energy

Design of Branch Predictor Simulator (March 2012)

• Simulated gshare, bimodal and hybrid branch predictors for processor pipelines using Java

• Explored the trade-offs between minimizing misprediction rate and predictor cost in no. of bits for each predictor

Dynamic Instruction Scheduling Simulator(May 2012)

• Constructed a simulator for an out-of order superscalar processor based on Tomasulo’s algorithm using Java

• Found optimum combinations of Scheduling Queue size and no. of instructions fetched at a time which resulted in minimum IPC (Instructions per Cycle)

EDUCATION

M.S., Electrical Engineering

North Carolina State University, US

GPA: 3.27

2010-2012

B.E., Electronics and Communication Engineering

Delhi College of Engineering, India

70.61%

2004-2008

Contact this candidate