post silicon validation

Atul Srivastava

E-***, AKME BALLET APPAMT

Bangalore, India 560037

91-80-420***** (h); +91-956-***-**** (m)

*******@*****.***

SUMMARY

8+ years’ experience in Post Silicon Validation at System level varying from analog systems, low cost simple embedded systems to complex Power PC, Intel Processor’s and ARM based platforms

Hands-on experience on IP (USB, SD cards, HSIC, PLL, PFlash controller,NFC, Timers,ADAS,IOT,AM,FM,DAB, Analog Radio ) level validation at Power PC and ARM based SoCs

Hands-on experience on LauterBach, P&E debuggers and Intel Test Probe (ITB) debugger and validation debug over elf simulation setups with characteristic including EMC and EMI debug

Platform Validation for Ivy Bridge based Customer Reference Board, Board bring up, testing after assembly

Handled advanced features like Over Clocking, Dynamic Turbo, Power Management, etc

Power measurement of the SoC by enabling/disabling various interfaces at various PVT

Generating Design & Test plan Documents,power on,power sequencing and board bring up.

Hands-on experience in AT command programming of GPS/GSM Module (SIM300CZ)

APGD (Advance Post Graduate Diploma) in VLSI design from VEDANT (ISRO), SCL, Mohali

EDUCATION

PG Diploma in VLSI Design, VEDANT (An ISRO sponsored Instt.), 01/07 – 06/07

BE, Electronics and Telecommunications, Rajiv Gandhi Technical University, Bhopal, 06/06; 60%

EXPERIENCE

Black Pepper Technologies Pvt Ltd Present

Tech Lead

Scoping of validation activity, ownership for Qualcomm and H Micro based chips which is useful for cars,IOT and health care domain various IPs Validation at system level

Scoping the area for Turn Key projects in house.

Defining and driving characterization and qualification of Turn Key products and document the results.

Supporting the ramp-up of new products for all Semiconductor vendors like QC, APM etc

Developing the tracking mechanism for validation and testing for cross coverage scenarios of Low Power chips as per their technical specification.

Interaction with customer to get their specification and develop the plan for strategically to get their validation and system level testing.

Develop the plan for mixed signal level board brings up activities and execution as well.

Freescale Semiconductor Pvt Ltd 06/13 – 02/15

Lead Design Engineer

Responsible for IP level protocol validation along with responsible for board bring up and trouble shooting of virgin silicon

Post Si Validation of Power PC based SoC for Car body and dash board (08/14 – Present)

Scoping of validation activity, ownership of SoC for car body and dash board for various IPs Validation at system level

oThis involves, test plan development, test plan review and approval from design & architecture team, test implementation & test case development

oReviewing the vendor test plan & give feedbacks and as per feedbacks from stake holders making use cases scenarios like adaptive light dimming mechanism for high end cars, etc.

oValidation activity includes Code level, Register level and hardware level validation on board and debug the issues made elf simulation environment to debug the IP related issues

Power drain for Car’s SoC based on power PC Validation (01/14 – 08/14)

Scoping of validation activity, ownership of power drain SoC which is useful for cars various IPs Validation at system level

oThis involves, test plan development, test plan review and approval from design & architecture team, test implementation & test case development

oReviewing the vendor test plan & give feedback and as per feedbacks from stake holders making use cases scenarios like adaptive light dimming mechanism for high end cars etc.

oWorking as Validation lead for whole cobra55 Validation activity. Code level, Register level and hardware level validation on board and debug the issues made elf simulation environment to debug the IP related issues

Calypso6M SoC based on power PC Validation (05/13 – 01/14)

Scoping of validation activity, ownership of Calypso for various IPs Validation at system level

oThis involves, test plan development, test plan review and approval from design & architecture team, test implementation & test case development

oReviewing the vendor test plan & give feedbacks

oWorking as Validation lead for whole Calypso6M Validation activity

oCode level, Register level and hardware level validation on board and debug the issues

Intel Technologies India Pvt Ltd, Bangalore 05/11 – 05/13

Validation Engineer

Validate the Chipset in a customer use case environment at platform level to identify the issues before hand

oThe group is responsible for Intel chipsets dedicated to Personal computing for mobile & desktops

Power Management IC(PMIC) Validation (05/12 – 05/13)

Scoping of validation activity, ownership of PMIC Validation at system level

oThis involves, test plan development, test plan review and approval from design & architecture team, test implementation & test case development

oReviewing the vendor test plan & give feedbacks

oWorking as Validation lead for whole PMIC Validation activity

oRegister level validation on board and debug the issues

Performance and Thermal validation of Intel chips (05/11 – 05/12)

Ownership of Thermal Validation in which Dynamic power thermal framework is key ingredient

oOwned the complete activity starting from Scoping, test plan development, test case implementation and execution

oFound issue in turbo implementation in BIOS code, unique defect triggered a code fix and found many issues, which were work around by the developer or silicon team

Worked on Power Management IC validation

oThis involved system level validation of all feature set of PMIC at board level as well System integrity level

Responsible for Anti-Theft, Media Vault, OTP (One Time Password), Treasure Lake (Access management), Hudson Lake (encrypted Hard disk management), Over clocking, Intel Turbo Boost, DPTF (Dynamic Power Thermal Framework) & CPTT (Converge Platform Thermal Throttling) Technology Validation

Use of ITP debugger & MSR utility for reading & writing configuration values

System level debugging in Windows 7 environment for Chipset products

Supporting the automation infrastructure and perform regression test on different platform configurations

Tuning of BIOS configuration to set up different parameters for chipset configurations

Execute and debug concurrency, CPU matrix and Power Management tests on chipset platforms

Knowledge on PC and chipset (north/south bridge) system architecture.

Published paper on Implementation of Power Management IC for Ultrabook Platform; IJERA (ISSN: 2248-9622 http://www.ijera.com/)

Satyam Software Solution Pvt Ltd, Noida 09/08 – 04/11

Validation Engineer

Bsquare (US); Tablet PC based on OMAP3530 (Texas Instruments) (03/10 – 10/10)

Board bring up, testing after assembly

Power measurement of the board by enabling/disabling various interfaces

Developed Test cases for serial protocol testing – UART, I2C, SPI, Timer, WDOG, GPIO etc

oThe tests are verified on available ARM board(dev kit)

oWhen the actual board comes, with minimal changes same test case can be re-used

EMC; LPC2129 Based in house developed Board for Industrial Application (06/09 – 12/09)

Debugging of ARM microcontroller application boards

oThe objective was to validate the Board level connections and chipset functionally

oThe peripherals validated are: PLL, UART, GPIO, Timers, ADC, I2C. SPI, WDO

oThe development and debugging was done using Keil uVision toolset and H-JTAG/H-Flasher

oAlso used ARM Project Manager

oPerform physical inspection of finished product

oPrepared Test Plans and Test Result Report

In House Production; GSM MODULE (01/09 – 04/09)

Involved in board level testing and debugging of HW and SW

To check the electrical testing of SIM points and data points

Involved in initial startup issues for connectivity of GSM Module with STB

GSM Module connected to hyper terminal and through AT Commands, Module was debugged

Used LCD & Hyper Terminal for debugging the GSM Module

TruSound Pvt Ltd, (Ahuja Radios Company), Noida 09/07 – 09/08

Graduate Engineer Trainee

Responsible for “Zero Defect Delivery” of Audio Mixers, conference Systems, Amplifiers with Built-In Cassette Players/ Recorders Addressing Systems

Involved measurements of Audio parameters given below:

oSignal to Noise Ratio

oTotal Harmonic Distortion

oFrequency Response of Audio Products and validate against their specifications

Also working towards ISO 9001:2000 Certification

Handling calibration job for all equipments at site level

VEDANT Institute of VLSI Design, SCL, Mohali 01/07 – 06/07

Design, development and implementation of Keyboard Controller Integrated with VGA Controller on Xilinx Spartan FPGA

oThis design takes input from normal SQUIRT keyboard through 6 pin PS/2 connector fitted on SPARTAN 3 Development kit

oThe data is processed through KBD Controller implemented on FPGA and then fed to VGA controller implemented on same FPGA. Another VGA Connector mounted on board outputs VGA signals to a VGA Monitor

oThe coding is done in Verilog –HDL and verification was done on Cadence NC Simulator

oThe design was implemented on Xilinx Spartan 3 FPGA

SKILLS

Technologies:

Anti-Theft, Media Vault, OTP, Treasure Lake, Hudson Lake, over clocking, Intel Turbo Boost, DPTF (Dynamic Power Thermal Framework) & CPTT (Converge Platform Thermal Throttling) Technology, Power Management Integrated Circuit and RTD3 with Connected standby of Windows, ADAS(Advance driver assistance system, IOT(Internet of things),NFC

Protocols:

PFLASH controller, USB, SD Cards, HSIC, I2C, SPI, RS-232, DFS, PIT, STM, RTC

Languages:

C & ARM Assembly language,TCL Programming

Compilers:

Metro works Code warrior, Keil, GNU ARM Compiler

Hardware Platform:

x86 Platforms, ARM7xx, SIM 300CARM7, ARM STM32xx Cortex M3

Lab Equipment:

Audio Precision System, Oscilloscope, Distortion Meter, USB protocol analyzer, Function generators,Labview etc.

In Circuit Debugger:

ITP-II, H-JTAG, Multi ICE, LauterBach, P&E

Operation systems:

Win 7/8 and win blue, Android especially with power management and APIs functional validation with patch debugging, Bug-zilla, JIRA

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