SELVAKUMAR R.

No *, Raj Villa, *st Cross, RMV *nd Stage, Dollars Colony, Bangalore - 54

Email: acrodf@r.postjobfree.com

Mobile: +91-991*******

CAREER OBJECTIVE

Seeking a challenging position in well established company that offers professional growth and ample opportunity to learn and enrich my competencies in my profession.

QUALIFICATION

PG Diploma in VLSI Design

o2006-2007 Sandeepani School of VLSI Design, Training division of CoreEL Technologies – Authorized Xilinx Training Center.

M.E. Applied Electronics

o2002–2004, Karunya Institute of Technology (Affiliated to Anna University, Chennai) Coimbatore. First class

B.E Electrical and electronics Engineering

o1997–2001, M.V.Jayaraman College of Engineering (Affiliated to Bangalore University) Bangalore. First Class with Distinction

EXPERIENCE

Total Experience: 9+ Years of experience in the field of VLSI design.

During this tenure time was dedicated in developing and delivering training in VLSI Design for students and corporate engineers at all levels. Creating test plan, test cases for evaluating new features of EDA tool, providing feedback to developers, customer support, and research & product development was part of the work culture.

Currently I am working as Corporate Application Engineer - II for Synopsys (I) Pvt. Ltd. Bangalore since January 2012.

1– Year of Experience in CoreEL technologies (I) Pvt. Ltd. Bangalore as Senior Member Technical Staff from the period of January 2011 to December 2011.

4 – Years of Experience in VLSI System Design Centre, MSRSAS, Bangalore from the period of January 2007 to January 2011.

1– Year of Experience in Atria Institute OF Technology, Bangalore as a lecturer from the period of April 2004 to November 2005.

Current Responsibilities

Product feature testing

Customer support

Creating Application notes with user examples

QoR Improvement - suggestions to R&D for the QoR improvement

Monitoring Regressions

Qualifying third party P&R tools.

New device support

Customer & AC training on new features

Debugging logic issues

Creating test plans, Requirement Specs, Creating test cases & validation of test cases, reporting the issues through issue document

PROFESSIONAL SUMMARY

Good hands on RTL coding (Verilog HDL)

Good experience in FPGA Design flow

Worked on RTL Synthesis and Static Timing Analysis

Good Knowledge on ASIC Front end

PROJECT DETAILS

Title: Pre-Adder input mode, Constant mode and Coefficient mode Support for ArriaV/CycloneV/ StratixV

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Title: M18x19 signed multiplier support for ArriaV/CycloneV

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Title: Pre-Subtractor Support for StratixV/ArriaV/CycloneV

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Title: Dynamic Add-Sub & Negate Support for StratixV/ArriaV/CycloneV

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Timing driven Register unpacking for DSPs for StratixV/ArriaV/

Title: Synplify Pro Feature Evaluation – DSP &RAM resource management for STRATIX V

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Description: This project is to evaluate the autobudgeting & resource management feature of DSPs & RAMs/ROMs for the STRATIX5 FPGA using attribute syn_allowed_resources with/without compile points on top module or submodules. The autobudgeting will be done in the pre mapping stage of synthesis and the same budget will be honored by Mapper

Title: Synplify Pro Feature Evaluation – rw_check UI switch handling for RAM inference

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Description: This project is to evaluate the new rw_check UI switch in synplify Pro. When rw_check is enabled, the synthesis tool inserts bypass logic around the RAM to prevent a simulation mismatch between the RTL and post-synthesis simulations. If user knows that design has RAM that read and write to the same address simultaneously, rw_check switch can be enabled to insert bypass logic. When switch is disabled, the synthesis tool does not insert bypass logic around the RAM.

Title: Synplify Pro Feature Evaluation – Memory initialization enhancement for Altera Intel Hex file

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Description: This project is to evaluate memory initialization hex file generated by Synplify Pro. For Altera devices RAM/ROM/Seqshift initialization hex file generated by Synplify Pro was incorrect for memory depth more than 64k. The values in hex file from 1 to 65536 locations are correct, but after 65536 locations Synplify Pro writes the value continuously (i.e. without header) till the maximum depth of the memory which is not correct. Due to incorrect hex file during clearbox call for RAM / ROM / Seqshift depth more than 64k “parameter mem_init<n>, “n” is from 0 to memory depth” are initialized to zero after 64k locations in vqm/vm/vhm file because of this vm/vo/vhm/vho simulation are failing.

Title: Synplify Pro Feature Evaluation –Loadable Accumulator Support in DSP for STRATIXV (ongoing)

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Description: This project is to evaluate Synplify Pro mapper to support accumulator inference with/without dynamic load in DSP for STRATIX V.

Title: Synplify Pro Feature Evaluation – Pre-Adder Support in DSP for STRATIXV (ongoing)

Company: Synopsys (I) Pvt. Ltd., Bangalore.

Description: This project is to evaluate Synplify Pro mapper to support the pre-adder feature that includes coefficient mode, input mode, square mode and Constant mode in DSP for STRATIX V.

Title: Design and Development of Integrated FPGA Based Digital Beamforming Transceiver System for AURA (Proposed)

Company: Aeronautical Development Agency, Bangalore.

Description: Digital beamforming is a powerful technique to enhance antenna performance. DBF system is a potential candidate for the Adaptive Interference Cancellation in the aerospace applications. The hardware design and implementation of a DBFTS is based on the modeling of the DBF transmitter and receiver system. The digital architecture is developed such that the transmitter and receiver modules of DBFTS can function independent of each other. The computation of beamforming weighting functions can either be common to transmitter and receiver or it can be computed independently. On a need basis, the DBFTS can be switched between the DBF and DNS modes. Development and Verilog modeling of functional Block diagram of Tx and Rx modules of DBFTS along with the desired specifications of the individual blocks/sub blocks. Synthesize the individual blocks and sub blocks of Tx and Rx modules

Title: Implementation of Activity Detector on FPGA

Company: Kavveri Telecom Products Ltd, Bangalore.

Description: Peak detection and band code generation logic was designed as per specification for amplitude measurement. Designed Peak detection and band code generation logic were modeled using HDL and was verified using test bench. Implemented the designed peak detection and band code generation logic on Virtex –II Pro FPGA with ADC interfaces and programmable connections according to the specifications

CORPORATE TRAININGS

Corporate Training Topics

Company / Venue

Verilog and FPGA Design

ISRO Satellite Centre (ISAC), Bangalore, November 2010

FPGA Synthesis

Satish Dhawan Space Centre (SDSC) SHAR, Sriharikota, October 2010

Verilog HDL and FPGA Design

Tejas Networks,Bangalore, Augist 2010

FPGA Synthesis

FPGAS for signal processing and Communication, MSRSAS. March -2010

FPGAs for Signal processing

2nd National Conferences on Advances in Communication and Computing, September - 2009

FPGA Design

Tejas Networks,Bangalore, Augist 2009

FPGA Design

Institute for Electronics and Telecommunication Engineering, Bangalore, 2008

FPGA Design

Tejas Networks,Bangalore, September 2008

Verilog HDL

Tejas Networks,Bangalore in July 2007

FPGA Design

Tejas Networks,Bangalor in August 2007

PERSONAL SKILL

Hard Working and Sincere.

Positive Attitude, Determined.

Good Counselor.

Able to handle people in a very efficient way.

SOFT SKILLS

Presentation and Public Speaking

Training & Facilitation

Documentation

PERSONAL PROFILE

Name Selvakumar R.

Father’s Name T. Ramasethu

Date of birth 24-03-1979

Nationality Indian

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