Page * of *

RESUME

Name:

Thomas W. Lofte

***** * ********* ****

Home Address:

Lodi, CA, 95240-9749

Tel

acroal@r.postjobfree.com

: 510-***-****

Career Objective:

with leading edge company in wireless, wireline, data communications, Interested in a senior technical/project management position telecommunications, or multimedia technologies.

Professional/Consulting History:

06/2004 to present:

Consulting Engineer, Lodi, CA.

Currently working as consulting Senior Embedded Systems Engineer at Audience Inc, Mountain View, CA. Involved in supporting Audience audio noise reduction chip (Tensilica) sets for wireless cell phones including chip set operating system and audio algorithm application code debugging and performance testing.

Previously worked as a consulting Principal DSP Engineer for Harmonic Inc, San Jose, CA. Responsible for porting existing and new real-time wideband audio codecs (Dolby AC3/EAC3, MPEG2/4 AAC/LC/HE, DTS) to new hardware DSP (TI TMS320C6747) based audio/video compression product. Involved in hardware/firmware interface definitions, hardware/firmware testing, hardware board bring up and FPGA functional definition. Previously worked as a Technical Lead DSP/Audio Algorithms for Cisco in Milpitas, CA. Developing, implementing, and testing real-time DSP processor (TI TMS320DM6467) based firmware for performing multichannel IP/RTP packet based transcoding, transrating, voice activity detection (VAD), frame erasure concealment (FEC), automatic gain control (AGC), speech enhancement & noise reduction techniques, and network echo cancellation (ITU-T G.168). Testing and improving speech quality (ITU-T P.862) for a multichannel wireline video/audio communications and conferencing product.

Previously worked as an DSP contract engineer at Northrop Grumman DENRO office in Elkridge, MD. Upgrading and reverse engineering real-time DSP TMS320C5510 VOIP firmware to support new multichannel wireless/wireline VOIP communication system features. Updated VAD, frame erasure concealment, jitter buffer timing recovery, standard and non-standard RTP packets for packet inbound and outbound processing, and new audio codec support. Updating firmware tasks to run under preemptive multitasking TI DSP/BIOS.

Previously worked as a technical DSP consultant for a legal law firm involved in a lawsuit concerning a full duplex speakerphone product using TI TMS320C32/TMS320C6713B devices. Provides technical DSP expertise on product technology include line echo cancellation techniques, acoustical echo Page 2 of 5

cancellation, microphone array beam forming, audio noise reduction, comparison of various DSP acoustical signal processing algorithms and reverse firmware engineering efforts for litigation. Previously worked (Phonic Ear, Petaluma, CA) as a DSP consultant on a real-time multi-channel acoustical feedback suppression and cancellation algorithm using a TI TMS320C5502 device. Provides technical expertise regarding algorithm improvement and enhancements to improve acoustical feedback suppression.

Previously worked (Siport, Santa Clara, CA) on designing sigma delta ADC hardware decimation filters for the wireless physical (PHY) layer of an SOC digital radio receiver (DAB) product. Previously worked at (Texas Instruments/San Jose, CA) on hardware verification of an SOC ADSL/VDSL chip set. Performing ASIC functional prototype hardware emulation using Xilinx Virtex FPGA and Cadence QuickTurn hardware emulator to verify physical layer signal processor signaling, channel encoder/decoder, and HDLC path of a high speed ADSL/VDSL chip set. Completed assignment (PixelWorks,Campbell,CA) working on multichannel audio compression decompression algorithm Dolby AC3 for a high performance embedded Linux multimedia system on chip (SOC). Algorithm implementation includes conversion of floating point algorithm to fixed point processor implementation, test vector functional verification, optimization, and real time functional testing on SOC.

06/2002 to 06/2004:

Responsible for the overall technical systems engineering and systems FPGA/ASIC hardware architecture of a wireless dual band GSM/GPRS SOC communications chip. Managed a team of 12 system engineers (RF, DSP, Protocol, FPGA), developing both a circuit switched voice and packet switched cell phone chip set. Developed the system specifications (PRD/SRD) for the transport layer

(physical/protocol stack) and application layer (circuit switched voice, packet switched Internet) including physical layer synchronization (automatic gain control AGC, automatic frequency control AFC, carrier search, channel equalization, channel coding & decoding, receiver timing recovery), protocol stack (RLC/MAC, LLC, SNDCP, HDLC, RR, CM, MM, GMM), and wireless Internet applications including TCP/UDP/IP, HTTP, FTP, POP3, SMTP, IMAP4, LDAP, PKI, SSL/TLS, WAP2.0, VOIP (PoC), XML, MMS, and multimedia (JPEG, H.263/H.264 MP3) compression. Provided hand on technical expertise and direction to project engineering team during RF, FPGA digital/analog hardware, DSP firmware and RISC protocol software systems integration. Involved in PCB board layout, fab, and debugging. Worked on analog GSM/GPRS base band converter specification.

Director of Systems Engineering, Via Communications, Fremont, CA. 01/2002 to 06/2002

team for a SOC ADSL communications chip set product. Managed team of 10 DSP senior and junior engineers. Responsibilities included setting team technical objectives and deliverable goals,

: Manager, Digital Signal Processing, Centillium Communications, Fremont, CA. Responsible for overall technical direction and project management for DSP firmware development schedules, tracking team performance, setting individual goals and objectives, developing firmware design and documentation standards, giving performance reviews and interviewing prospective DSP team members. Helped DSP team develop ADSL physical layer receiver timing, receiver carrier synchronization and receiver adaptive channel equalization. Provided weekly DSP project status and performance to senior company management and participated in new business activities in wireline and wireless communications.

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10/2001 to 01/2002:

Positioning System) SOC hardware and firmware solution into a GSM digital handset. Architecture study included technical, cost, and power requirements for A-GPS handset integration. Consulting Engineer, Enuvis Inc, South San Francisco, CA. I performed system architecture and technical requirements study for integrating a unique assisted GPS (Global 04/2001 to 10/2001:

Principal DSP Engineer, ComSilica, Inc., Fremont, CA. Responsible for direction and management of small team (2) DSP firmware for SOC IEEE802.11a wireless OFDM LAN chip set. Designed MIMD/SIMD instruction set for a proprietary programmable high speed (200MHZ) DSP for real time TX/RX signal processing functions. Developed bit exact, fixed point C/Matlab simulation for receiver OFDM demodulation, receiver timing recovery, receiver frequency recovery, and receiver adaptive equalizer. Worked on system engineering and integration plans for WLAN hardware development and debugging.

06/96-03/2001:

Responsible for developing, implementing and testing GSM mobile phone physical layer requirements on an SOC ARM/DSP processor. Developed and implemented real time preemptive multitasking DSP Principal DSP Engineer, Nixxo Technologies, Co, Santa Clara, CA. micro kernel, transmitter burst building, non-linear receiver equalization algorithm, automatic frequency control (AFC), automatic gain control (AGC), receiver coarse/fine timing synchronization, DTMF encoder, and RPELTP speech vocoder. Designed and directed DSP firmware development for GSM voiceband handset product. Directed and managed the DSP firmware/hardware team (4) in GSM handset product. Provided SOC system engineering for hardware architecture design for a GSM/GPRS circuit and packet switched handset. Involved in PCB development board layout, fab, and debugging. Performed Altera/Xilinx FPGA hardware Verilog simulation to verify ASIC functional prototype hardware design. Participated in GSM cell phone RF and audio laboratory system testing. 02/96 to 05/96:

Implemented real time speech compression algorithm, ITU-T G.723, on a micro programmable video compression chip. Evaluated hardware architectures, algorithms to support real time speech Member of Technical Staff, 8x8, Inc., Santa Clara, CA. compression, video compression (H.263), acoustical echo cancellation for video conferencing. 10/95 to 03/96:

completed on part time consulting basis.

DSP Consultant. Completed real time speech compression algorithm (RPE-LTP) on 16 bit fixed point DSP (DSP Group OAK) for GSM digital cellular phone product. Effort 03/95 to 02/96:

System level architecture studies on DSP/NSP system for a multimedia product involving audio, telephony, modem, fax, digital simultaneous voice and data (DSVD), ISDN, and video/image/audio

(H.263, JPEG, MP3) compression. Evaluated third party DSP data/fax modem software. Sr. DSP Communications Engineer, Diamond Multimedia Systems, San Jose, CA. 10/92 to 03/95:

Responsible for design, development, and testing of modems for the dial up telephone network. Implemented ITU V.27ter (4800 bps) and V.29 (9600 bps) fax modem using a digital signal Senior Scientist, Phylon Communications, Fremont, CA. processor chip (ADI-2115). Implemented ADPCM voice compression and data compression algorithm’s for a modem chip set product. Implemented physical layer for V.32terbo modem (19200 bps) for high speed data communication product. V.32terbo modem and voice compression used in simultaneous voice and data (SVD) multimedia product. Project engineer on a V.34 high speed development modem involved in receiver timing recovery, receiver carrier recovery, and adaptive Page 4 of 5

channel equalization (28800 bps) used in a multimedia product. 09/88 to 10/92:

Previously consulted (Paramed Technology) in the research and development of a real time continuous non-invasive blood pressure monitoring system employing statistical pattern recognition and estimation Consulting Engineer, Fremont, CA.

techniques. Responsible for developing/testing embedded firmware algorithms for performing sensor data preprocessing and feature extraction.

Previously consulted (Develco/Baker-Hughes) in the design and development of an acoustical modem for oil well communications. Responsible for developing, simulating, and testing digital signal processing algorithms for real time acoustical channel signal detection and characterization. Algorithms use modern parametric modeling approaches and classical for signal detection and system identification. Also developed adaptive filter algorithms for acoustical signal improvement. Developed acoustical channel models based on linearized wave propagation modeling. Acoustic models used to develop channel probing algorithms, and test receiver carrier and receiver timing synchronization.

Previously consulted (KLA/San Jose, CA) in the design and implementation of real time digital image processing firmware algorithms for an industrial automation system. Responsibilities included the design, development, and testing of proprietary image and object recognition algorithms for an automated semiconductor inspection system.

01/88 to 09/88:

Intercon/ORI Systems Corp, Sunnyvale, CA. Employed as a Senior System engineer. Involved in the conceptual design of a low cost, transportable HF/VHF/UHF COMINT signal collection system for US/Foreign military and government agency users. Performed marketing studies and research to identify potential users/customers for a low cost throwaway signal collection product. Developed real-time firmware and tracking algorithms for a SIGINT/COMINT signal processor.

08/86 to 01/88:

TCI, Fremont, CA. Employed as a Senior System engineer. Responsible for the design, development, and testing of a real time digital signal processor for wide band and narrow band high frequency (HF) COMINT signal collection and signal exploitation. Additional duties included the analysis, electromagnetic (EM) modeling, simulation and implementation of HF antenna systems for radio direction finding (DF) applications. Additional responsibilities included RFP proposal writing and presenting technical briefings to customers.

04/84 to 08/86:

ARGOSystems, Sunnyvale, CA. Employed as a Senior Engineer. Technical responsibilities included evaluating customer requirements for real time signal collection system products involving signal classification and signal exploitation. Small team (3) program manager on an IR&D study effort involving technical approaches for automated identification and recognition of communication signals. Participated in RFP teams for advanced signal collection systems product definition.

09/81 to 04/84: ESL/TRW Systems, Sunnyvale, CA. Employed as a Senior Engineer. Responsibilities included the analysis, design, test and integration of signal processing subsystems for tactical signal collection system products. Designed, implemented, and integrated microprocessor based real time firmware algorithms for a hybrid VHF/UHF signal classifier product employing statistical pattern recognition techniques. Contributed to an implementation of a real-time high Page 5 of 5

resolution direction finding (DF) algorithm for a multiple VHF/UHF antenna system. Participated in RFP teams for advanced signal collection systems.

12/79 to 09/81:

STS/Ricoh, San Jose, CA. Employed as a Senior Engineer. Responsibilities included the verification and validation of real-time DSP design for a microprocessor based digital modem product for dial up telephone modem applications.

10/78 to 12/79:

Kaiser Electronics, San Jose, CA. Employed as a Senior Systems Engineer. Technical duties included modeling and model validation of airborne optical display subsystems. 10/72 to 10/78:

Lockheed Missiles and Space Company, Sunnyvale, CA. Employed as a Senior Research Engineer in missile guidance and flight controls. Responsibilities included the analysis, design, and synthesis of digital flight control subsystems for ballistic missiles. Worked on missile control system implementation and testing using 6 DOF (degrees of freedom) aerospace missile simulations in real-time emulation with flight hardware. Evaluated new technologies (TOA/GPS) and estimation techniques (Kalman filtering) for advanced missile guidance and flight control systems. Participated in RFP teams for advanced missile guidance systems. Worked as Satellite Analyst supporting real time satellite commanding, satellite health and status, satellite telemetry analysis, orbit launch determination, on orbit test sequences and trained as an orbit ephemeris analyst. Chip Experience:

TI TMS320C25, TMS320C30, TMS320C5502, TMS320C5510, TMS320C6202, TMS320C6713B, TMS320DM6467, TMS320C6747, OMAPL137, Motorola DSP56001, Analog Devices ADSP-2105, 2115, 2171, 2181, 21X1,21020, DSP Group OAK/TeakLite, ARC4/6, ARM7/ARM9, ARM Cortex A8, MIPS 3K/4K, Centillium Sigma DSP, LSILogic ZSP400/500, Xilinx Virtex FPGA, and Equator BSP15/16, Tensilica Xtensa LX2 core. Operating system experience includes VRTX, Nucleus, TI DSP/BIOS, embedded Linux, and proprietary kernel. Language experience includes RISC/DSP assembly, C/C++, Algol, Jovial, ADA, Fortran, microcode. CAD Tools Experience:

Matlab/Simulink, Mathematica, Cadence SPW, System View, MathCad, NEC (Numerical Electromagnetic Codes), Adobe Framemaker, Microsoft Word, Excel, PowerPoint, PVCS, CVS, ClearCase, Perforce, SDL, UML, ModelSim, SystemVerilog/Verilog, QuickTurn hardware emulator, Xilinx ISE, PADS-PCB, AutoCad, Orcad, LabView, Comsol Multiphysics, Red Hat Linux (RHEL), Suse Linux (SLED), TI Code Composer, Octave, Satellite Tool Kit (STK), GoldWave, Audacity, Tensilica Xtensa Xplorer. Various ARM, ARC, MIP, Tensilica RISC emulators and TI DSP emulators.

Wireless/Wireline/Video/Audio Tools Experience:

TAS 4500/5600 RF Multipath channel emulator,

Spirent ADSL Line (DLS400) and Noise emulator (DLS5200), Agilent E5515C GSM/GPRS/EGPRS basestation emulator, Rohde/Schwarz CRTU-G GSM/GPRS/EGPRS mobile phone tester, Sage 960B IP packet monitor, Audio Precision AP2, WireShark, NVision NV9601 Video Router, Dolby Digital Audio Encoder DP567. Experienced with bench top DSO/MSO scopes, logic analyzers, network analyzers, DVM's, signal generators, RF signal analyzers, RF signal generators,. Educational Background:

San Jose State University 01/73 to 01/74. Graduate level courses in electrical engineering, mechanical engineering and mathematics.

University of Oklahoma BSEE, June 1970.

Professional References: Available upon request.

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